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| product structure silicon monolithic integrated circuit this product is not designed for protection against radioactive rays . 1 / 96 tsz02201 - 0q4q0ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 . f eb .201 5 rev.0 0 1 tsz22111 ? 14 ? 001 www.rohm.com system pmic for battery powered systems BD71805MWV g eneral d escription the BD71805MWV is a single chip power management ic for battery - powered por table devices. it integrates 4 bucks , 3 ldos, 2a single - cell linear charger, ovp, coulomb counter, rtc, 32 khz crystal circuitry and 3 gpos . f our highly efficient 2.5mhz step - down converters supply power to the application p rocessor as well as system peripherals such as ddr memory, wireless modules, and touch controller. the r egulator to the processor cor e sup por ts dvs. the regulators maintain high efficiency over a wide range of current loads by sup por ting both pfm and pwm modes. h igh switching frequency allows the use of smaller and cheaper inductors and capacitors. features ? 4 buck converters: - 1 - 2 0 00 ma buck - 3 - 1 00 0 ma bucks ? 3 ldos (general purpose) - 3 - 300 ma ldos ? ldo for ddr r eference v oltage ? ldo for secure non - volatile storage (snvs) ? single - cell linear lib charger with 30v - ovp - selectable c harging v oltage : 3. 72 to 4.3 4 v - programmable c harge c urrent : 100 to 2000ma - dcin over voltage protection - battery over voltage protection - support battery supplement mode - battery short circuit detection ? voltage measurement for t hermistor - bias v oltage o utput for e xternal t hermistor ? embedded coulomb c ounter for battery fuel gauging - 15 - bit ? - adc with e xternal c urrent s ense r esistor (10 m, 1%) - 1 - sec cycle, 2 8 - bit a ccumulation - coulomb count while charging/discharging ? battery monitoring and alarm output - under v oltage a larm while d ischarging - over d ischarge c urrent a larm - over/ u nder t emperature a larm - programmable t hresholds and t ime d urations - automatic low voltage mode (battery protection) 3.5v detection : interrupt to processor to ask user plug - in 3.3v detection : interrupt to processor to indicate battery critically lo w condition ? real time clock with 32.768khz crystal oscillator - 32.768khz c lock o utput (open d rain or cmos o utput s electable ) ? 3 gpos (open d rain or cmos o utput s electable ) ? power control i/o - power on/off c ontrol i nput - standby i nput for s witching on / standby m ode - reset input to reset hung pmic - power on reset output ? i2c i nterface applications ? e - book reader ? portable media players ? portable navigation devices key specifications ? i nput v oltage r ange (dcin) : 3.5 v to 28 v ? i nput v oltage r ange (vin,vsys) : 3.3 v to 5.5v ? i nput v oltage r ange (dvdd) : 1.5 v to 3.4 v ? off current : 25 a ( typ ) [rtc+ coulomb counter+ ldo_snvs+ 32kosc only ] ? operating temperature range : - 40 c to +85 c package w (typ) d (typ) h (max) uqfn64 m v8080 8 . 0 mm x 8 .0mm x 1.0mm status of this document the english version of this document is formal specification. a customer may use this translation version only for a referenc e to help reading the formal version. if there are any differences in translation version of this documen t formal version takes priority .
2 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv typical applications f igure 1 . typical applications 1 (master control mode) figure 2 . typical applications 2 (slave control mode) epd pmic i2c epd pmic ldo _snvs (always on) core1 dv ref ldo_ d v ref buck 1,2 arm, soc, pu buck4 high, nvcc33 ldo 2 ddr (lpddr2) wifi touch i/o 3. 15 v ldo 3 nvcc18 nvcc12, nvcc_dram snvs 3v 1. 3 75 v 3.15 v 1.8 v 1.2 v rtc + 32khz - osc xtal core2 i/o 1.2 v 1.8 v 0.6 v (?*dvrefin) dvrefin lib charger ovp dcin power on/off sequencer coulomb counter 3 - gpo ldo 1 2.5 v buck3 sd emmc 3. 15 v 3. 15 v 3. 15 v gpo gpo gpo power on/off control i.mx (i.mx6sololite) power key pwron pmic_on_req 3. 3 v epd pmic i2c epd i.mx (i.mx6sololite) pmic ldo _snvs (on/off) core1 dv ref ldo3 buck1 arm, soc, pu buck4 high, nvcc33_io ldo1 ddr (lpddr2) wifi nvcc_1p2v nvcc18_io snvs 1.8v 1.425 v 3.3 v 1.2 v rtc + 32khz - osc xtal core2 i/o 1.2 v 1.8 v 0.6 v (?*dvrefin) lib charger ovp dcin power on/off sequencer coulomb counter 3 - gpo buck3 sd emmc 3. 3 v 3. 3 v 3. 3 v gpo gpo gpo power key pwron ldo2 3.3v r r 3.3v buck2 1.2v nvcc_dram touch i/o 3 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv block diagram figure 3 . ic b lock d iagram (master control m ode) v d d _ a r m _ i n v d d _ s o c _ i n v d d _ h i g h _ i n n v c c 3 3 _ i o w i f i e m m c o t h e r s v d d _ p u _ i n b u c k 1 1 . 4 2 5 v 2 0 0 0 m a b u c k 4 1 . 8 v 1 0 0 0 m a b u c k 3 3 . 3 v 1 0 0 0 m a v i n u v l o t s d 4 . 7 u f p v i n 1 l x 1 f b 1 p g n d 1 2 . 2 u h 1 0 u f 4 . 7 u f p v i n 4 l x 4 f b 4 p g n d 4 2 . 2 u h 1 0 u f 4 . 7 u f p v i n 3 l x 3 f b 3 p g n d 3 2 . 2 u h 1 0 u f 4 . 7 u f v s y s v s y s v s y s v s y s b u c k 2 1 . 2 v 1 0 0 0 m a l d o _ d v r e f d v r e f i n * 0 . 5 v 1 0 m a l d o 1 1 . 2 v 3 0 0 m a v o 2 g n d t 1 1 u f v o 1 v i n l 1 1 u f 1 u f p v i n 2 l x 2 f b 2 p g n d 2 2 . 2 u h 1 0 u f 4 . 7 u f v o d v r e f ( n . c . ) 1 u f l d o 2 3 . 3 v 3 0 0 m a n v c c _ d r a m l p d d r 2 ( 1 . 2 v ) o t h e r s d d r - v r e f d v r e f i n ( n . c . ) g n d g n d v o 3 1 u f l d o 3 3 . 3 v 3 0 0 m a v s y s 1 0 u f b a t 1 0 u f c h g r e f 5 . 1 k t s g n d c h g l i b - c h a r g e r i c h g = 2 a m a x o v p < 3 0 v 1 u f d c i n c h g l e d c o u l o m b c o u n t e r b a t t p b a t t m b u c k 3 v s y s v s y s b a t t e r y p a c k 1 0 m n v c c _ 1 p 2 v d c i n v s y s v d d _ s n v s _ i n 1 u f l d o _ s n v s 3 . 0 v 2 5 m a d v d d c o n t r o l i 2 c p o w e r c n t s d a s c l i n t b p o r s t a n d b y p w r o n r t c v o s n v s 1 8 p f x i n 3 2 k 3 2 k h z o s c x o u t 3 2 k 1 8 p f c l k 3 2 k o u t 3 2 . 7 6 8 k h z - x t a l r e s e t i n b g p o 1 g p o 2 g p o g p o 3 m s s e l s n v s c a p n v c c 1 8 _ i o l p d d r 2 ( 1 . 8 v ) o t h e r s v s y s v i n l 2 1 u f i o ( d e f a u l t : o f f ) i o ( d e f a u l t : o f f ) v s y s s n v s c a p 1 0 k 1 0 0 k 2 . 7 k 1 0 k 1 0 k 1 0 0 k 1 0 0 k 0 . 0 1 u f c p o u t b u c k 1 b u c k 4 b u c k 3 b u c k 2 b u c k 4 t d k n t c g 1 6 3 j f 1 0 3 f t 1 s s e i k o - e p s o n f c - 1 3 5 4 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv block diagram - continued figure 4 . ic b lock d iagram (slave control mode) v d d _ a r m _ i n v d d _ s o c _ i n v d d _ h i g h _ i n n v c c _ 3 v 3 _ i n p e r i p h e r a l e p d v d d _ p u _ i n b u c k 1 1 . 3 7 5 v 2 0 0 0 m a b u c k 2 1 . 3 7 5 v 1 0 0 0 m a b u c k 3 3 . 1 5 v 1 0 0 0 m a v i n u v l o t s d 4 . 7 u f p v i n 1 l x 1 f b 1 p g n d 1 2 . 2 u h 1 0 u f 4 . 7 u f p v i n 2 l x 2 f b 2 p g n d 2 2 . 2 u h 1 0 u f 4 . 7 u f p v i n 3 l x 3 f b 3 p g n d 3 2 . 2 u h 1 0 u f 4 . 7 u f v s y s v s y s v s y s v s y s v o 2 b u c k 4 1 . 2 v 1 0 0 0 m a l d o _ d v r e f d v r e f i n * 0 . 5 v 1 0 m a l d o 1 2 . 5 v 3 0 0 m a v o 2 g n d t 1 1 u f v o 1 v i n l 1 1 u f 1 u f p v i n 4 l x 4 f b 4 p g n d 4 2 . 2 u h 1 0 u f 4 . 7 u f v o d v r e f 1 u f l d o 2 1 . 8 v 3 0 0 m a l p d d r 2 _ c o r e 2 d d r - v r e f 1 u f d v r e f i n g n d g n d v o 3 1 u f l d o 3 1 . 2 v 3 0 0 m a v s y s 1 0 u f b a t 1 0 u f c h g r e f 5 . 1 k t s g n d c h g l i b - c h a r g e r i c h g = 2 a m a x o v p < 3 0 v 1 u f d c i n c h g l e d c o u l o m b c o u n t e r b a t t p b a t t m b u c k 3 n v c c _ 1 2 n v c c _ d r a m v s y s v s y s b a t t e r y p a c k 1 0 m p e r i p h e r a l d c i n v s y s v d d _ s n v s _ i n 1 u f l d o _ s n v s 3 . 0 v 2 5 m a d v d d c o n t r o l i 2 c p o w e r c n t s d a s c l i n t b p o r s t a n d b y p w r o n r t c v o s n v s 1 8 p f x i n 3 2 k 3 2 k h z o s c x o u t 3 2 k 1 8 p f c l k 3 2 k o u t 3 2 . 7 6 8 k h z - x t a l r e s e t i n b g p o 1 g p o 2 g p o g p o 3 m s s e l s n v s c a p n v c c _ 1 8 l p d d r 2 _ c o r e 1 b u c k 3 v i n l 2 1 u f v s y s s n v s c a p 1 0 k 2 . 7 k 1 0 k 1 0 k 0 . 0 1 u f c p o u t b u c k 1 b u c k 2 b u c k 3 b u c k 4 v o 2 v o 2 v o 2 c o i n 1 0 0 t d k n t c g 1 6 3 j f 1 0 3 f t 1 s s e i k o - e p s o n f c - 1 3 5 5 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv pin configuration figure 5 . pin configuration (top view) 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 5 1 5 2 5 3 5 4 5 5 5 6 5 8 5 9 5 7 6 0 6 1 6 2 6 3 6 4 1 6 1 5 3 2 3 1 3 3 3 4 4 9 5 0 l x 1 p g n d 1 f b 1 v o s n v s g n d c l k 3 2 k o u t c h g l e d s d a s c l d v d d x o u t 3 2 k s t a n d b y f b 2 p g n d 2 r e s e t i n b g n d l x 2 x i n 3 2 k p v i n 2 m s s e l g p o 1 g p o 2 v o d v r e f d v r e f i n c p o u t f b 4 p g n d 4 l x 4 g p o 3 p v i n 1 v i n v i n l 2 v o 2 v o 1 v i n l 1 i n t b p o r g n d t 1 f b 3 p g n d 3 p g n d 3 l x 3 l x 3 v o 3 p v i n 3 p v i n 3 n c b a t t m b a t t p c h g r e f t s v b a t v b a t v s y s v s y s d c i n d c i n p v i n 4 c h g g n d p v i n 1 s n v s c a p p g n d 1 l x 1 p w r o n 6 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv pin description s table 1 . BD71805MWV pin description pin no. pin name. i/o function 1 pvin4 i input power supply for buck4 2 chgled o open - drain charging s tatus indication o utput 3 dcin i dcin power supply 4 dcin i dcin power supply 5 vsys o sys tem supply output 6 vsys o system supply output 7 vbat i /o charger power stage output and battery voltage sense input 8 vbat i /o charger power stage output and battery voltage sense input 9 ts i battery pack t hermistor voltage sense 10 chgref o intern al reference for the lib charger 11 battp i current sense input (battery pack side) 12 battm i current sense input (ground side) 13 chggnd - ground for charger 14 nc - n o connection 15 pvin3 i input power supply for buck3 16 pvin3 i input power su pply for buck3 17 lx3 o switch node connection for buck3 18 lx3 o switch node connection for buck3 19 pgnd3 i power ground for buck3 20 pgnd3 i power ground for buck3 21 fb3 i output voltage feedback for buck3 22 gndt1 - ground for test 23 por o pow er on reset output 24 intb o open drain interrupt signal to processor 25 vinl1 i ldo input for ldo1 26 vo1 o ldo output for ldo1 27 vo2 o ldo output for ldo2 28 vinl2 i ldo input for ldo2, ldo3 29 vo3 o ldo output for ldo3 30 vin i input power suppl y 31 pvin1 i input power supply for buck1 32 pvin1 i input power supply for buck1 33 lx1 o switch node c onnection for buck1 34 lx1 o switch node connection for buck1 35 pgnd1 - power ground for buck1. 36 pgnd1 - power ground for buck1. 7 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv pin descrip tions - continued table 2 . bd7180 5 mwv pin descriptions (continued) pin no. pin name. i/o function 37 fb1 i output voltage feedback for buck1 38 snvscap o ldo output for secure non - volatile storage (requires capacitor) 39 vosnvs o ldo output for secure non - volatil e storage 40 gnd - signal ground 41 clk32kout o 32.768khz clock output (open drain or cmos output selectable) 42 sda i/o i2c data line (open drain) 43 scl i i2c clock 44 dvdd i power supply for i2c interface 45 xout32k o 32.768khz - xtal output 46 xin 32k i 32.768khz - xtal input 47 pvin2 i input power supply for buck2 48 lx2 o switch node connection for buck2 49 resetinb i reset input to shutdown BD71805MWV 50 pgnd2 - power ground for buck2 51 fb2 i output voltage feedback for buck2 52 gnd - si gnal ground 53 pwron i power on/ o ff control input 54 standby i standby input signal for switching the on and sta ndby mode s 55 mssel i master or slave mode selector 56 gpo1 o output for general purpose (open drain or cmos output selectable) 57 gp o2 o output for general purpose (open drain or cmos output selectable) 58 gpo3 o output for general purpose (open drain or cmos output selectable) 59 vodvref o ldo output for ddr - vref 60 dvrefin i ldo input for ddr - vref 61 cpout o charge pump output fo r ovp 62 fb4 i output voltage feedback for buck4 63 pgnd4 - power ground for buck4 64 lx4 o switch node c onnection for buck4 8 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv pcb layout recommendations figure 6 . pcb layout recommendations (top view) t o b o t t o m l a y e r l c b l c b l c l c l l c b c l t o b o t t o m l a y e r t o b o t t o m l a y e r t o b o t t o m l a y e r t o b o t t o m l a y e r c l t o b o t t o m l a y e r t o b o t t o m l a y e r c c c c c c c c c c x t a l c c b t o b o t t o m l a y e r c c c c r r r r r r r r b d 7 1 8 0 5 b u c k 3 b y b o t t o m l a y e r b u c k 1 b y b o t t o m l a y e r b u c k 2 b y b o t t o m l a y e r b u c k 4 b y b o t t o m l a y e r b u c k 3 b y b o t t o m l a y e r l d o 2 b y b o t t o m l a y e r s n v s b y b o t t o m l a y e r l d o 3 b y b o t t o m l a y e r l d o 1 b y m i d l a y e r v o d v r e f b y m i d l a y e r 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 5 1 5 2 5 3 5 4 5 5 5 6 5 8 5 9 5 7 6 0 6 1 6 2 6 3 6 4 1 6 1 5 3 2 3 1 3 3 3 4 4 9 5 0 l x 1 p g n d 1 f b 1 v o s n v s g n d c l k 3 2 k o u t c h g l e d s d a s c l d v d d x o u t 3 2 k s t a n d b y f b 2 p g n d 2 r e s e t i n b g n d l x 2 x i n 3 2 k p v i n 2 m s s e l g p o 1 g p o 2 v o d v r e f d v r e f i n c p o u t f b 4 p g n d 4 l x 4 g p o 3 p v i n 1 v i n v i n l 2 v o 2 v o 1 v i n l 1 i n t b p o r g n d t 1 f b 3 p g n d 3 p g n d 3 l x 3 l x 3 v o 3 p v i n 3 p v i n 3 n c b a t t m b a t t p c h g r e f t s v b a t v b a t v s y s v s y s d c i n d c i n p v i n 4 c h g g n d p v i n 1 s n v s c a p p g n d 1 l x 1 p w r o n 9 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv description of blocks 1. high efficiency buck converter s (buck1 C 4) and ldo s BD71805MWV step down converters operate at fixed frequency of 2. 5mhz and employ p ulse w idth m odulation (pwm) at mo derate to heavy load current . at light load current , a converter would automatically enter power save mode and operate in pulse frequency modulation (pfm). during pwm operation, the converter use s a unique fast response voltage mode controller scheme w ith feed - forward input voltage to achieve good l ine and l oad r egulation, thus allowing the use of small ceramic input and output capacitors. at the beginning of each clock cycle initiated by the clock signal, the high side mosfet switch is turned on . the current flows from the input capacitor via the high side mosfet switch through the inductor to the output capacitor and load. during this phase, the current ramps up until the pwm comparator trip caus ing the control lo gic to turn off the switch. the current limit comparator will also turn off the switch in case the current limit of the high side mosfet switch is exceeded. t he low side mosfet rectifier is t urned on and the inductor current ramp s down after a dead time preventing shoot - through current . the current flows now from the inductor to the output capacitor and to the load. it returns back to the inductor through the low side mosfe t rectifier. the next cycle will again be initiated by the clock signal turning off the low side mosfet rectifier and turning on the on the high side mosfet switch. table 3 . BD71805MWV output power rails (master control mode) BD71805MWV output i.mx6 sololite usage example power supply initial output voltage load max adjustable range buck1 arm / soc/pu pvin1 1. 425v 200 0ma 0.8 to 2.000 v (25mv step) [ dvs ] buck2 nvcc_dram / lpddr2(1.2v) / others pvin2 1. 2 v 10 00ma 0.8 to 2.000 v (25mv step) [ dvs ] buck3 high / nvcc33_io/ wifi / emmc / others pvin3 3. 3 v 1 000ma 2.6 to 3.35v (50mv step) buck4 nvcc18_io / lp ddr 2 (1.8v) / others pvin4 1. 8 v 10 00ma 1.0 to 2.7v (50mv st ep) vo1 (ldo1) nvcc_1p2v vinl 1 1.2 v 30 0ma 0.8 to 3.3 v ( 50 mv step) vo2(ldo2) io (default:off) vinl 2 3.3 v 30 0ma 0.8 to 3.3 v (5 0 mv step) vo3(l d o 3) io (default:off) vinl 2 3.3 v 30 0ma 0 .8 to 3.3 v (5 0 mv step) vodv ref ddr_vref (default:off) vin 0.5*dvrefin 10ma 0. 4 to 1. 00v (dvrefin= buck2) (note1) vo snvs snvs vin 3.0v 25ma fixed (note1) when vodvref is not in use , please open dvrefin and vo dvref . table 4 . BD71805MWV output power rails (slave control mode) bd71 805mwv output i.mx6 sololite usage example power supply initial output voltage load max adjustable range buck1 arm pvin1 1.375v 2000 ma 0.8 to 2.000 v (25mv step) [ dvs ] buck2 soc/pu pvin2 1.375v 10 00ma 0.8 to 2.000 v (25mv step) [ dvs ] buck3 high / nvcc33 _io peripheral, epd pvin3 3.15v 1 000ma 2.6 to 3.35v (50mv step) buck4 lp ddr 2(1.2v) pvin4 1.2v 1 000ma 1.0 to 2.7v (50mv step) vo1( ldo1 ) peripheral vinl 1 2.5 v 30 0ma 0.8 to 3.3 v ( 50 mv step) vo2( ldo2 ) nvcc18_io / lpddr2(1.8v) vinl 2 1. 8 v 30 0ma 0.8 to 3 .3 v (5 0 mv step) vo3( ldo 3) nvcc_1p2v / nvcc_dram vinl 2 1.2v 30 0ma 0 .8 to 3.3 v (5 0 mv step) vodv ref ddr_vref v in 0.5*dvrefin 10ma 0. 5 to 1. 35 v (dvrefin=buck4) snvs cap snvs vin 3.0v 25ma fixed 10 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv table 5 . BD71805MWV output power rail s # buck x on [ 5 :0] stby[ 5 :0] off[ 5 :0] buck1 [v] buck2 [v] buck3 [v] buck4 [v] ldo x [ 5 :0] ldo1 [v] ldo2 [v] ldo3 [v] 0 0 0 0000 0.800 0.800 2.600 1.000 0 0 0000 0 . 800 0 . 800 0 . 800 1 0 0 0001 0.825 0.825 2.650 1.050 0 0 0001 0 . 8 50 0 . 8 50 0 . 8 50 2 0 0 0 010 0.850 0.850 2.700 1.100 0 0 0010 0 . 900 0 . 900 0 . 900 3 0 0 0011 0.875 0.875 2.750 1.150 0 0 0011 0 . 9 50 0 . 9 50 0 . 9 50 4 0 0 0100 0.900 0.900 2.800 1.200 0 0 0100 1 . 0 00 1 . 0 00 1 . 0 00 5 0 0 0101 0.925 0.925 2.850 1.250 0 0 0101 1. 05 0 1. 05 0 1. 05 0 6 0 0 0110 0.950 0.950 2.900 1.300 0 0 0110 1. 100 1. 100 1. 100 7 0 0 0111 0.975 0.975 2.950 1.350 0 0 0111 1. 15 0 1. 15 0 1. 15 0 8 0 0 1000 1.000 1.000 3.000 1.400 0 0 1000 1. 200 1. 200 1. 200 9 0 0 1001 1.025 1.025 3.050 1.450 0 0 1001 1. 25 0 1. 25 0 1. 25 0 10 0 0 1010 1.050 1.050 3.100 1.500 0 0 1010 1. 300 1. 300 1. 300 11 0 0 1011 1.075 1.075 3.150 1.550 0 0 1011 1. 35 0 1. 35 0 1. 35 0 12 0 0 1100 1.100 1.100 3.200 1.600 0 0 1100 1. 400 1. 400 1. 400 13 0 0 1101 1.125 1.125 3.250 1.6 50 0 0 1101 1. 4 50 1. 4 50 1. 4 50 14 0 0 1110 1.150 1.150 3.300 1.700 0 0 1110 1.5 00 1.5 00 1.5 00 15 0 0 1111 1.175 1.175 3.350 1.750 0 0 1111 1. 55 0 1. 55 0 1. 55 0 16 0 1 0000 1.200 1.200 1.800 0 1 0000 1. 600 1. 600 1. 600 17 0 1 0001 1.225 1.225 1.850 0 1 0001 1. 6 50 1. 6 50 1. 6 50 18 0 1 0010 1.250 1.250 1.900 0 1 0010 1.7 00 1.7 00 1.7 00 19 0 1 0011 1.275 1.275 1.950 0 1 0011 1 . 7 50 1 . 7 50 1 . 7 50 20 0 1 0100 1.300 1.300 2.000 0 1 0100 1 . 8 00 1 . 8 00 1 . 8 00 21 0 1 0101 1.325 1.325 2.050 0 1 0101 1 . 8 50 1 . 8 50 1 . 8 50 22 0 1 0110 1.350 1.350 2.100 0 1 0110 1 . 9 00 1 . 9 00 1 . 9 00 23 0 1 0111 1.375 1.375 2.300 0 1 0111 1 . 9 50 1 . 9 50 1 . 9 50 24 0 1 1000 1.400 1.400 2.350 0 1 1000 2 .00 0 2 .00 0 2 .00 0 25 0 1 1001 1.425 1.425 2.400 0 1 1001 2 . 0 5 0 2 . 0 5 0 2 . 0 5 0 26 0 1 1010 1.450 1.450 2.450 0 1 1010 2 . 1 00 2 . 1 00 2 . 1 00 27 0 1 1011 1.475 1.475 2.500 0 1 1011 2 . 15 0 2 . 15 0 2 . 15 0 28 0 1 1100 1.500 1.500 2.550 0 1 1100 2. 200 2. 200 2. 200 29 0 1 1101 1.525 1.525 2.600 0 1 1101 2 . 25 0 2. 25 0 2. 25 0 30 0 1 1110 1.550 1.550 2.650 0 1 1110 2. 300 2. 300 2. 300 31 0 1 1111 1.575 1.575 2.700 0 1 1111 2. 35 0 2. 35 0 2. 35 0 32 1 0 0000 1.600 1.600 1 0 0000 2. 400 2. 400 2. 400 33 1 0 0001 1.625 1.625 1 0 0001 2. 4 50 2. 4 50 2. 4 50 34 1 0 0010 1.650 1.650 1 0 0010 2.5 00 2.5 00 2.5 00 35 1 0 0011 1.675 1.675 1 0 0011 2.550 2.550 2.550 36 1 0 0100 1.700 1.700 1 0 0100 2.600 2.600 2.600 37 1 0 0101 1.725 1.725 1 0 0101 2.650 2.650 2.650 38 1 0 0110 1.750 1.750 1 0 0110 2.700 2.700 2.700 39 1 0 0111 1.775 1.775 1 0 0111 2.750 2.750 2.750 40 1 0 1000 1.800 1.800 1 0 1000 2.800 2.800 2.800 41 1 0 1001 1.825 1.825 1 0 1001 2.850 2.850 2.850 42 1 0 1010 1.850 1.850 1 0 1010 2.900 2.900 2.900 11 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv table 6 . bd71805m wv output power rails (continued) # buck x on [ 5 :0] stby[ 5 :0] off[ 5 :0] buck1 [v] buck2 [v] buck3 [v] buck4 [v] ldo x [ 5 : 0] ldo1 [v] ldo2 [v] ldo3 [v] 43 1 0 1011 1.875 1.875 1 0 1011 2 . 9 50 2 . 9 50 2 . 9 50 44 1 0 1100 1.900 1. 900 1 0 1100 3 . 0 00 3 . 0 00 3 . 0 00 45 1 0 1101 1.925 1.925 1 0 1101 3. 05 0 3. 05 0 3. 05 0 46 1 0 1110 1.950 1.950 1 0 1110 3. 100 3. 100 3. 100 47 1 0 1111 1.975 1.975 1 0 1111 3. 15 0 3. 15 0 3. 15 0 48 1 1 0000 2.000 2.000 1 1 0000 3. 200 3. 200 3. 200 49 1 1 0001 1 1 0001 3. 25 0 3. 25 0 3. 25 0 50 1 1 0010 1 1 0010 3. 300 3. 300 3. 300 51 1 1 0011 1 1 0011 52 1 1 0100 1 1 0100 53 1 1 0101 1 1 0101 54 1 1 0110 1 1 0110 55 1 1 0111 1 1 0111 56 1 1 1000 1 1 1000 57 1 1 1001 1 1 1001 58 1 1 1010 1 1 1010 59 1 1 1011 1 1 1011 60 1 1 1100 1 1 1100 61 1 1 1101 1 1 1101 62 1 1 1110 1 1 1110 63 1 1 1111 1 1 1111 voltage step 25mv 25mv 50mv 50mv - 50mv 50mv 50mv initial voltage of master control mode initial voltage of slave control mode 12 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv 2. power on/off sequence (1) master control mode figure 7 . power - on/off sequence (master control mode) table 7 . power rails turn - on/off delays (master control mode) min. typ. max. settling time of rtc clock trtc - 100.0 - ms depend on crystal pwron valid time t0 400.0 - - ms turn on delay of vosnvs t1 - 0.24 - ms turn on delay of buck1 t2 - 0.49 - ms turn on delay of buck2 t3 - 0.73 - ms turn on delay of buck3 t4 - 0.98 - ms turn on delay of buck4 t5 - 1.22 - ms turn on delay of ldo1 t6 - 1.46 - ms turn on delay of por t7 - 2.44 - ms turn off delay t10 - 0.49 - ms condition unit spec symbol parameter b a t t e r y v s y s p w r o n t 0 b u c k 1 ( 1 . 4 2 5 v ) f o r v d d _ a r m , v d d _ p u , v d d _ s o c t 1 b u c k 2 ( 1 . 2 v ) f o r n v c c _ d r a m , l p d d r 2 ( 1 . 2 v ) , o t h e r s b u c k 3 ( 3 . 3 v ) f o r v d d _ h i g h _ i n , n v c c 3 3 _ i o , w i f i , e m m c o t h e r s p o r l d o 1 ( 1 . 2 v ) f o r n v c c _ 1 p 2 v l d o 2 ( 3 . 3 v ) f o r i o ( d e f a u l t : o f f ) t 4 v o d v r e f ( d v r e f i n * 0 . 5 v ) f o r d d r - v r e f b u c k 4 ( 1 . 8 v ) f o r n v c c 1 8 _ i o , l p d d r 2 ( 1 . 8 v ) , o t h e r s l d o 3 ( 3 . 3 v ) f o r i o ( d e f a u l t : o f f ) t 7 t 1 0 s t a n d b y o n s t a n d b y o n s e q u e n c e o f f o n o f f s e q u e n c e o f f c o n t r o l e d b y i m x 6 m o r e t h a n 0 . 2 s e c c o u n t b y p m i c p o w e r s t a t e u v l o c l k 3 2 k o u t c o u l o m b c o u n t e r _ e n d i s a b l e i 2 c _ e n e n a b l e d i s a b l e w h e n t 0 i s l e s s t h a n 4 0 0 m s e c . , p o w e r o n s e q u e n c e d o e s n t s t a r t . s t a n d b y m o d e t f s t r t c v o s n v s ( 3 . 0 v ) f o r s n v s _ i n t 2 s n v s c a p r e s t a r t e n r e s i s t e r ) s h u t d o w n s h u t d o w n f r o m i m x 6 c o n t r o l e d b y i m x 6 t 3 t 5 t 6 b d 7 1 8 0 5 b a t t e r y i m x 6 s w 2 s c l d c i n v o s n v s = 3 v p o r p w r o n s w 1 r e s e t i n d c i n v b a t v s y s v i n p w r _ k e y _ i n t # b u c k 1 = 1 . 4 2 5 v v d d _ a r m _ i n , v d d _ s o c _ i n , v d d _ p u _ i n b u c k 2 = 1 . 2 0 0 v n v c c _ 1 v 8 _ i / o b u c k 3 = 3 . 3 0 0 v v d d _ h i g h _ i n , n v c c _ 3 v 3 _ i n , n v c c _ 3 v 3 i o , e p d _ 3 v 3 , o t e r s b u c k 4 = 1 . 8 0 0 v n v c c _ d r a m , l p d d r 2 _ 1 v 2 _ p o w e r l d o 1 = 1 . 2 0 0 v l d o 2 = 3 . 3 0 0 v n v c c _ 1 p 2 l d o 3 = 1 . 2 0 0 v s n v s _ i n s d a s t a n d b y i n t b m s s e l b u c k 3 s d a s c l s t a n d b y p o r i n t b s n v s c a p 0 . 2 s e c 13 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (2) slave control mode figure 8 . power - on/off sequence (slave control mode) table 8 . power rails turn - on/off delays (slave control mode) b a t t e r y v s y s s w 1 t 0 b u c k 1 ( 1 . 3 7 5 v ) f o r v d d _ a r m b u c k 2 ( 1 . 3 7 5 v ) f o r v d d _ p u , v d d _ s o c b u c k 3 ( 3 . 1 5 0 v ) f o r v d d _ h i g h , n v c c _ 3 v 3 , p e r i p h e r a l p o r l d o 1 ( 2 . 5 0 0 v ) f o r p e r i p h e r a l l d o 2 ( 1 . 8 0 0 v ) f o r n v c c _ 1 8 _ i o v o d v r e f ( b u c k 3 * 0 . 5 v ) f o r d d r - v r e f b u c k 4 ( 1 . 2 0 0 v ) f o r d d r t 1 0 s t a n d b y s t a n d b y m o d e o n s t a n d b y o n s l e e p o n s e q u e n c e o f f o n o f f s e q u e n c e o f f l e s s t h a n 0 . 2 u s e c p u l s e c o u n t b y i m x 6 m o r e t h a n 0 . 2 s e c c o u n t b y i m x 6 p o w e r s t a t e u v l o c l k 3 2 k o u t c o u l o m b c o u n t e r _ e n d i s a b l e i 2 c _ e n e n a b l e d i s a b l e w h e n t 0 i s l e s s t h a n 4 0 0 m s e c . , p o w e r o n s e q u e n c e d o e s n t s t a r t . s l e e p m o d e t r t c t 1 s n v s _ c a p f o r s n v s _ i n m o r e t h a n 1 s e c c o u n t b y i m x 6 s h u t d o w n s h u t d o w n p w r o n b u c k x _ o m o d e ( r e g i s t e r ) 2 0 1 3 . 0 9 . 3 0 b d 7 1 8 0 5 b a t t e r y i m x 6 s w 2 s c l d c i n s n v s c a p = 3 v p o r p w r o n s w 1 r e s e t i n b d c i n v b a t v s y s v i n o n o f f b u c k 1 = 1 . 3 7 5 v n v c c _ a r m _ i n b u c k 2 = 1 . 3 7 5 v n v c c _ 1 v 8 _ i / o b u c k 3 = 3 . 1 5 0 v v d d _ h i g h _ i n , n v c c _ 3 v 3 _ i n , n v c c _ 3 v 3 i o , e p d _ 3 v 3 , e p d , o t e r s b u c k 4 = 1 . 2 0 0 v n v c c _ d r a m , l p d d r 2 _ 1 v 2 _ p o w e r l d o 1 = 2 . 5 0 0 v l d o 2 = 1 . 8 0 0 v n v c c _ 1 p 2 l d o 3 = 1 . 2 0 0 v s n v s _ i n s d a s t a n d b y i n t b m s s e l p m i c _ o n _ r e q s d a s c l s t a n d b y p o r i n t b v d d _ s o c _ i n , v d d _ p u _ i n s n v s c a p t 2 t 3 l d o 3 ( 1 . 2 0 0 v ) f o r n v c c _ 1 p 2 v t 4 t 7 f r o m i m x 6 min. typ. max. settling time of rtc clock trtc - 100.0 - ms depend on crystal pwron valid time t0 400.0 - - ms turn on delay of buck1 and 2 t1 - 0.24 - ms turn on delay of buck3 and ldo1 t2 - 0.49 - ms turn on delay of buck4 and ldo4 t3 - 0.73 - ms turn on delay of ldo3 and vodvref t4 - 0.98 - ms turn on delay of por t7 - 2.44 - ms turn off delay t10 - 0.49 - ms unit spec symbol parameter condition 14 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv 3. master control modes operation bd7180 5 mwv operate s at master control mode when mssel is set to low. bd7180 5 mwv master mode has four power states or modes: on, off, standby, and shutdown. figure 9 shows the state transition diagram along with the conditions to enter and exit from each state. figure 9 . power states transitions (mast er control mode) description of states is provided in the following section. note that v sys must exceed vsysmax (initial=3.5v) to power up. additionally, i2c co ntrol is not possible in shutdown mode , nonetheless , the interrupt signal, intb, is active in standby, and on states. table 9 . voltage rails on/off for r espective p ower s tates (master control mode) a n y s t a t e i c s h u t d o w n r e s e t i n b = l o r t r e m a l s h u t d o w n o f f 3 . 2 v Q v s y s v s y s Q 2 . 9 v o n p w r o n = l > 0 . 2 s e c o r d c i n o k = h o r r t c a l a r m s t a n d b y s t a n d b y = h s t a n d b y = l v s y s Q 3 . 3 v ( i s s u e i n t b ) 3 0 s e c t i m e r - o u t ( a u t o s h u t d o w n ) o r r e s t a r t e n ( r e g i s t e r ) = 1 h o n ( l i m i t e d ) p w r o n = l > 1 0 s e c o r r e s t a r t e n ( r e g i s t e r ) = 1 h p w r o n = l > 1 0 s e c o r r e s t a r t e n ( r e g i s t e r ) = 1 h v s y s Q 3 . 3 v ( i s s u e i n t b ) v s y s Q 3 . 3 v ( a u t o p o w e r o n / i s s u e i n t b ) o f f ( l o w - v o l t a g e ) 3 . 5 v Q v s y s i c s h u t d o w n ? u v l o b l o c k = o n ? r t c = o f f ? b a t t e r y m e a s u r e m e n t = o f f o f f / s t a n d b y / o n ? u v l o b l o c k = o n ? r t c = o n ? b a t t e r y m e a s u r e m e n t = o n p w r o n ( p o w e r k e y ) n o n - a c t i v e p w r o n ( p o w e r k e y ) a c t i v e state buck1 buck2 buck3 buck4 ldo1 ldo2 ldo3 dvref vosnvs i2c i/f shutdown off off off off off off off off off disable off off off off off off off off off off disable on on (pwm fix) on (pwm fix) on (pwm fix) on (pwm fix) on off off off output enable standby on (auto) on (auto) on (auto) on (auto) on off off off output enable 15 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (1) master control mode state s (a) shutdown mode when vsys falls below 2.9v , BD71805MWV enters shutdown mode . a thermal shutdown event also forces BD71805MWV into shutdown mode. in case of system hung up , setting resetinb to low will caus e the ic to s hut down . only the vsys voltage measurement block (uvlo) is powered during shutdown mode. all register s are cleared to initial data. to exit shutdown mode, vsys must exceed 3.2v. (b) o ff (low - voltage) mode BD71805MWV enters off (low - voltage) mode when vsys exceed 3.2v or after auto low power on event (automatically turns on when vsys falls below vsysmin (initial=3.3v)). in this mode, uvlo, rtc and battery measurement ( coulomb co unter) b locks are powered. no turn on event is accepted in this mode. to exit off (low - voltage) mode, vsys must exceed vsysmax (initial=3.5v). (c) off mode BD71805MWV enters off (low - voltage) mode after a turn - off event , wherein v sys exceeds vsysmax (initial=3.5v) . in this mode, uvlo, rtc and battery measurement ( coulomb counter) b locks are powered. por is asserted low in this mode . to exit off mode, a valid turn - on event is required. (d) on mode BD71805MWV enters on mode after a turn - on event. por is de - asserted high in this mode of operation. (e) on (limited) mode BD71805MWV enters on (limited) mode after auto low power on event. to exit on (limited) mode, set restarten to high. restarten register is in access ible for more than 30 seconds while forced to exit this mode until it enters off (low - voltage) mode. (f) s tandby mode BD71805MWV enters standby mode when stand by pin is asserted. this mode is typically used for low - power mode of operation. when in standby mode, power consumption is reduced by lowering regulators output voltages, or disabling some regulators, etc. such configuration is pre - programmed through the i2c interface. to exit standby mode , standby pin is de - asserted . (2) master control mode events (a) turn on events from off mode, bd7180 5 mwv is powered on by turn on event s . bd7180 5 mwv master mode has three turn on events. see power stage trans itions diagram (figure 9 ). following are more detailed descriptions of turn on events. ? if pwron signal is low (pulse width is 0.2 seconds or more ), bd7180 5 mwv will turn on. ? if dcinok signal is high (dcin is supplied with appropriate v oltage) , bd7180 5 mwv will turn on. ? if the a larm that is set in alm0 register is interrupted, bd7180 5 mwv will turn on. ? if vsys falls below vsysmin (initial:3.3v), bd7180 5 mwv will turn on (auto low power on event). when this event occur s , intb is asserted low, and the ic enter s on (limited) mode. (b) turn o ff events from o n or standby mode, bd7180 5 mwv is powered o ff by turn o ff event s . bd7180 5 mwv has three turn off events. see power stage transitions diagram (figure 9). follo wing are more detailed descriptions of turn on events. ? if pwron signal is low (pulse width is 10 seconds or more ), bd7180 5 mwv will turn o ff . ? if restarten register is set to high, bd7180 5 mwv will turn o ff . ? if 30 seconds elapse after enter ing on (limited) mode, bd7180 5 mwv will turn o ff . (c) thermal shutdown event (thermal protection) if the die temperature surpasses a given threshold, the thermal protection circuit will shut down bd7180 5 mwv to avoid damage. a turn - on event will not power on the pmic while it is in thermal protection. the part will remain in shutdown mode until the die temperature decreases below a given threshold. there are no specific interrupts related to this other than the warning interrupt. see p ower dissipation section for more detailed information. 16 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv 4. slave control modes operation BD71805MWV operate s at slave control mode when mssel is set to high. BD71805MWV has five power states or modes: on, off, sleep, standby, and shutdown. f igure 10 shows the state transition diagram along with conditions to enter and exit from each state. figure 10 . power states transitions (slave control mode) description of states is provided in the following section. note that v sys must exceed 3.2v to allow power up. additionally, i2c control is not possible in shutdown mode , nonethe less , the interrupt signal, intb, is active in sleep, standby, and on states. table 10 . voltage rails on/off for r espective p ower s tates (slave control mode) a n y s t a t e s h u t d o w n r e s e t i n b = l o r t e r m a l s h u t d o w n o f f 3 . 2 v Q v s y s v s y s Q 2 . 9 v o n p w r o n = h p w r o n = l a n d a l l b u c k x o m o d e = 0 s t a n d b y s t a n d b y = h s t a n d b y = l p w r o n = l a n d a l l b u c k x o m o d e = 0 s l e e p p w r o n = l a n d a n y b u c k x o m o d e = 1 p w r o n = h a n d a n y b u c k x o m o d e = 1 p w r o n = l a n d a l l b u c k x o m o d e = 0 p w r o n = l a n d a n y b u c k x o m o d e = 1 state buck1 buck2 buck3 buck4 ldo1 ldo2 ldo3 dvref snvscap i2c i/f shutdown off off off off off off off off off disable off off off off off off off off off output disable on on (pwm fix) on (pwm fix) on (pwm fix) on (pwm fix) on on on on output enable standby on (auto) on (auto) on (auto) on (auto) on on on on output enable sleep on (pfmfix) on (pfmfix) on (pfmfix) on (pfmfix) on on on on output enable 17 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (1) slave control mode states (a) shutdown mode when vsys falls below 2 .9v , BD71805MWV enters shutdown mode . a thermal shutdown event also forces BD71805MWV into shutdown mode. to reset the hung up system, assert resetinb to low causing the ic to s hut down . only vsys voltage measurement block (uvlo) is powered in this mode. all register s are cleared to initial data. to exit shutdown mode, vsys must exceed 3.2v. (b) off mode BD71805MWV enters off mode after a turn - off event. in this mode, snvs, uvlo, rtc and battery measurement ( coulomb counter) b locks are powered. por is asserted low in this mode . to exit off mode, a valid turn - on event is required. (c) on mode BD71805MWV enters on mode after a turn - on event. por is de asserted high in this mode of operation. (d) s tandby mode BD71805MWV enters standby mode when standby pin is asserted. this mode is typically used for low - power mode of operation. when in standby mode, power consumption is reduced by lowering regulators output voltag es, or disabling some regulators, etc. such configuration is pre - programmed through the i2c interface. to exit standby mode , standby pin is de - asserted . (e) sleep mode BD71805MWV enters sleep mode when pwron pin is de - asserted and any buck xo mode bit is set to high. in sleep mode, each regulator will use the settings programmed to its sleep mode registers, e.g., buck xomode for buck x . a ctivated regulators will maintain the settings for this mode until the next turn - on event. when in sleep mode, power consumption is reduced by lowering regulators output voltages , shifting regulators to pfm fixed mode, or disabling some regulators, etc. such configuration is pre - programmed through the i2 c interface. to exit sleep mode , pwron pin is asserted . (2) slave control mode events (a) t urn on events from off mode, BD71805MWV is powered on by turn on event s . BD71805MWV slave mode has two turn on events. see power stage transitions diagram (figure 10). following are more detailed d escription s of turn on events. ? if pwron signal i s high, BD71805MWV will turn on. ? if dcinok signal is high (dcin is supplied with appropriate voltage) , BD71805MWV will turn on. (b) turn o ff events from o n, standby or sleep mode, bd71 805mwv is powered o ff by turn o ff event s . BD71805MWV has two turn off events. see power stage transitions diagram (figure 10). following are more detailed descriptions of turn on events. ? if pwron signal is low when all buckxomode bit s are set to low, BD71805MWV will turn o ff . ? if vsys falls below 3.1v, BD71805MWV will turn o ff . (c) thermal shutdown event (thermal protection) if the die temperature surpasses a given threshold, the thermal protection circuit will shut down bd7180 5mwv to avoid damage. a turn - on event will not power on the pmic while it is in thermal protection. the part will remain in shutdown mode until the die temperature decreases below a given threshold. there are no specific interrupts related to this other th an the warning interrupt. see power dissipation section for more detailed information. 18 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv 5. dynamic voltage scaling (dvs) control buck1 and buck2 are support dynamic voltage scaling (dvs). during change in operation mode, buck1 and buck2 voltage s vary accordingly . output voltage is set by i2c registers as follows. (1) on mode : o utput voltage is set by buck1_on[5:0] for buck1 and buck2_on[5:0] for buck2. (2) standby mode : o utput voltage is set by buck1_st by[5:0] for buck1 and buck2_stby[5:0] for buck2. (3) sleep mode : o utput voltage is set by buck1_slp[5:0] for buck1 and buck2_slp[5:0] for buck2. slope speed is also set via i2c register by buck1_ramprate[1:0] for buck1 and buck_ramprate[1:0] for buck 2. figure 11 . dvs control image 1.375v down ramping up ramping 1.375v no ramping 1.100v 0.900v with power on sequence dvs setting (i2c register) min.0us power state buck1/2 v on =v stby =v slp =1.375v on sleep on on sequence v on =1.375v, initial delay(typ.10us) standby off 10mv/us 10mv/us 10mv/us 19 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv 6 . over voltage protection (ovp) block features ? single - input for the battery charger source: dcin ? 30v over voltage protection for dcin input. 7 . battery charger block features ? s upports battery insertion and removal detection ? jeita compliant battery charging profile with thermal control of charging current and voltage settings . this is achieved by measuring the temperature from the external thermistor (the initial setting of BD71805MWV is adjust ed to tdk ntcg163jf103ft1s) . ? supports battery supplement mode ? automatic or manual (software ) control of watch dog timer while pre C charging and fast - charging ? charger statuses or error conditions are indicated on chgled output (for led lighting) . (note) when a battery is removed and is conne cted, please use 3 - terminal battery including the thermistor. figure 1 2 . power state of battery charger a n y s t a t e s u s p e n d c h a r g e s t o p t r i c k l e c h a r g e p r e c h a r g e f a s t c h a r g e t o p o f f d o n e c h a r g e s t o p s h u t d o w n d c i n o k = l ( d c i n 3 . 2 v ) o r v s y s Q 2 . 9 v 3 . 2 v Q v s y s d c i n o k = h ( d c i n R 3 . 2 v ) v b a t > v p r e _ l o v b a t < v p r e _ l o v b a t > v p r e _ h i v b a t < v p r e _ h i i b a t < i c h g _ t e r m t i m e r 1 5 s e c . i b a t > i c h g _ t e r m v b a t < v b a t _ m n t t e m p e r r 4 t e m p e r r 5 t e m p e r r 1 t e m p e r r 2 t s d 4 t s d 1 t s d 2 t e m p e r r 3 t s d 3 t s d 5 b a t t e r r o r c h a r g e s t o p t i m e r > w d t _ f s t o r v b a t _ o v p t i m e r > w d t _ p r e o r v b a t _ o v p c h a r g e s t o p t o b a t e r r o r t i m e r > 1 2 0 m o r v b a t _ o v p t o b a t e r r o r t i m e r > 1 2 0 m o r v b a t _ o v p t o b a t e r r o r t i m e r > 1 2 0 m o r v b a t _ o v p t o b a t e r r o r v b a t _ o v p t o b a t e r r o r v b a t _ o v p b a t t a s s i s t 1 b a t t a s s i s t 2 b a t t a s s i s t 3 v s y s < v b a t v s y s > v b a t v s y s > v b a t v s y s < v b a t v s y s > v b a t ( a ) n o t t o s u s p e n d n o t t o s u s p e n d n o t t o s u s p e n d n o t t o s u s p e n d n o t t o s u s p e n d t i m e r > w d t _ p r e o r v b a t _ o v p b a t d e t c h a r g e s t o p v s y s < v b a t b a t d e t _ d o n e ( b ) b a t _ t e m p > 5 8 o r b a t _ t e m p < 2 b a t _ t e m p < 5 8 a n d b a t _ t e m p > 2 c h i p t e m p > 1 3 5 c h i p t e m p > 1 7 5 ( c h i p t h e r m a l s h u t d o w n ) ( a ) c h i p t e m p > 1 2 5 ( i l i m _ d c i n s e t 1 / 2 ) ( b ) h o l d c o n n e c t i o n w i t h o u t r e m o v i n g t h e b a t t e r y . 20 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv figure 1 3 . battery charger output control there are four watch dog timers to this ic. a) h igh temperature protection timer the high temperature protection timer is a timer to count when bat_temp[2:0]=3h and state of the temp_err1 or temp_err2 or temp_err5. this timer counts 1 in approximately 64 se conds and shifts to bter state after 121 counts. b) low temperature protection timer the low temperature protection timer is a timer to count when bat_temp[2:0]=5h and state of the temp_err1 or temp_err2 or temp_err5. this timer counts 1 in approximately 64 seconds and shifts to bter state after 121 counts. c) watch dog timer while pre - charging and trickle - charging when trickle - charge or pre - charge needs a charge state machine, this timer counts 1 for approximately 64 seconds and shifts to bter state after 121 counts. but the number of the counts is modifiable by changing register setting. (address44h wdt_pre) d) watch dog timer while fast - charging and t op off when fast - charge or topoff needs a charge state machine, this t imer counts 1 for approximately 64 seconds and shifts to bter state after 601 counts. but the number of the counts is modifiable by changing register setting. ( address 45h wdt_fst) this timer becomes the low temperature protection timer by changing register setting. (address42h cold_err_en) 42h:chg_set1 00xxxx11 01xxxx11 3bh:bat_temp[2:0] 4h 4h threshold to bter 3 3 3 3 240 240 240 240 -1 -1 -2 -2 -2 -2 -2 -2 1442 1442 1442 1442 1442 wdt_fst * 8 wdt_fst * 8 wdt_fst * 8 initial set value countdown value wdt_auto cold_err_en chg_en l h h h l h l h l h l l h h l fchg or toff l h h h h h h h h fchg or toff fchg or toff fchg or toff fchg or toff fchg or toff fchg or toff fchg or toff 34h:chg_state 00xxxx01 01xxxx01 00xxxx11 01xxxx11 00xxxx01 wdt_dis l l l 01xxxx01 l l l l l 4h 4h 0h or 1h or 2h or 6h 0h or 1h or 2h or 6h 0h or 1h or 2h or 6h 0h or 1h or 2h or 6h v b a t t i m e t r i c k l e c h a r g e p r e c h a r g e f a s t c h a r g e ( c c ) ( c v ) t o p o f f 1 5 [ s ] c h a r g e c u r r e n t b a t t e r y v o l t a g e i b a t v b a t c h g v p r e _ h i v p r e _ l o i p r e i t r i i f s t i f s t _ t e r m d o n e countdown value initial set value -1 -1 1 1 threshold to bter wdt_pre 122 3bh:bat_temp[2:0] 0h or 1h or 2h or 6h 0h or 1h or 2h or 6h h tchg or pchg 01xxxx11 l h h h tchg or pchg 00xxxx11 l l h chg_en 34h:chg_state 42h:chg_set1 wdt_dis wdt_auto cold_err_en 21 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (1) thermal control for charging c harging current is controlled by the battery temperature measured from the external thermistor. in low - temperature condition, charging current is reduced to half of t he setting value (ichg). figure 1 4 . charging current vs. battery temperature c harging voltage is also reduced by temperature and set by control registers. table 11 . charging voltage vs. battery temperature jeita temperature range voltage setting register t2 C C C f igure 1 5 . charging voltage vs. battery temperature 0 1/2 ichg ichg [ma] [c] 5c 2 c 10 c 13.0c 55.0c 58.0 c c h a r g i n g v o l t a g e t e m p e r r a t u r e o f b a t t e r y p a c k v b a t _ c h g 1 v b a t _ c h g 2 v b a t _ c h g 3 t 1 t 2 t 3 t 5 t 4 c h a r g i n g v o l t a g e t e m p e r r a t u r e o f b a t t e r y p a c k v b a t _ c h g 1 v b a t _ c h g 2 v b a t _ c h g 3 t 1 t 2 t 3 t 5 t 4 b t m p _ e n = 0 ( a d d r e s s 4 2 h b i t 2 ) b t m p _ e n = 1 ( a d d r e s s 4 2 h b i t 2 ) 22 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv 8 . coulomb counter block figure 1 6 . coulomb counter block diagram features ? 2 8 - bit coulomb counter for battery fuel gauging ? 1 5 - bit ? - adc measures the battery s charg e and discharg e current by means of an external current sense resistor (10m, 1%). ? c harging/ d ischarging amount integration period : 1sec ? coulomb counter value approaches the battery capacity when finished chargi ng . ? while discharging, a half - capacity alarm and a near - empty alarm can be output from intb terminal (1) functions and program m abilites (a) 2 8 - bit accumulator charge / discharge integration - current measurement range is 0 to 3 a for charging and discharging - current sampling rate is 1, 4, 8, or 16 hz. - the time base is from the external 32.768khz rtc clock. - upper 16 bits of 2 7 - bit coulomb counter can be read from host, max 11380 mah. - coulomb counter can be cleared by software command. - full charge capacity register can be either set by the coulomb counter when charging stop s or set from host. (b) two programmable event alarm output from intb pin - half - capacity discharge alarm - near - empty discharge alarm (c) al arm output control settings and status for appropriate event - threshold: 16 bits, automatically calculated or set from host - event status: 1 when the discharge amount exceeds the threshold, 0 when the discharge amount is less than th e threshold - alarm output enable: 1 for enabling alarm output / 0 for disabling it. - alarm output status: 1 indicates the alarm asserted / 0 indicates the alarm not asserted , and write to the bits to clear the status. battp battm intb 1 5 - bit ? 1 5 23 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv 9. 12 - bit adc (sar) block features ? 12 - bit successive approximation register a/d converter ? conversion period: 40 s ? input voltage range: 0. 6 to 5. 4 v (vbat for battery voltage monitor ) ? input voltage range: 0. 6 to 5. 4 v (v sys for system input voltage monitor ) ? input voltage range: 0. 2 to 1. 3 v ( vf for BD71805MWV die temperature monitor) ? input voltage range: 0. 2 to 1. 3 v (ts for battery temperature monitor ) ? input voltage range: - 30 m to 30 mv (battp for battery current monitor ) ? input voltage range : 2 to 16v (dcin for dcin voltage monitor) figure 1 7 . 12 - bit adc block diagr am 10. battery monitor block features ? monitoring the b attery condition and performance ? 12 - bit sar - adc measures the battery output voltage, battery charg e /discharg e current with an external current sense resistor (higher rate than the ? - adc), and battery temperature with an external thermistor (the i nitial setting of BD71805MWV is adjust ed to tdk ntcg163jf103ft1s ) ,. ? the battery temperature information is provided for the battery charger. ? d edicated output pin for alarm/int errupt with several pro g rammable event s ? bias voltage output for the external thermistor ? automatic low voltage mode (battery protection) - 3.5v detection : interrupt to processor to ask user plug in - 3.3 v detection : interrupt to processor to indicate batt ery critically low condition. after 30sec, processor initiate s power down. power key is locked out. (1) functions and program m abilites (a) battery voltage monitoring to detect over discharging - voltage measurement range is 0.6 to 5. 4 v - under volta ge threshold is programmable - under voltage event can assert the alarm output - over voltage is detected by the battery charger while charging (b) battery temperature monitoring to detect over/under temperature event - battery temperature is measured by the voltage of the external ntc thermistor with an external pull - up to bias voltage. (common circuit with the battery charger) - over/under temperature threshold is programmable - over/under temperature event can assert the alarm output - software is abl e to enable/disable battery temperature monitoring (c) programmable event alarm with several events output from intb pin - under voltage alarm while discharging - over/under temperature alarm while charging /discharging - over voltage alarm while charging. - battery maintenance voltage (vbatment) across below/over threshold (d) alarm output control settings and status for the appropriate event - threshold and time duration - event status : 1 when the value exceeds the threshold, / 0 when the value is less than the threshold - alarm output enable: 1 for enabling alarm output / 0 for disabling it. - alarm output status: 1 indicates the alarm asserted / 0 indicates the alarm not asserted, and write to the bits to clear the status. 1 2 - b i t a d c ( s a r ) c o n t r o l l o g i c i n t e r r u p t c o n t r o l a f e & s w i t c h 1 2 v b a t v s y s v f t s b a t t p v b u s 24 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv 11 . real time clock (rtc) block features ? rtc is driven by 32.768 khz oscillator and provides alarm and time keeping functions to the nearest second. ? time information in seconds, minutes, and hours. ? calen dar information in day, month, year, and day of the week. ? alarm interrupt sent at the time and day which are programmed into registers. ? key status flags retained through reset and power cycle in rtc backup flags, e.g., reason for power - on or power - off ? eigh t bit registers have values that are retained even after the main battery resets to zero when transitioning or until shutdown state. ? eight bit registers have a lock control that once written will lock the resistor until shutdown state is entered. ? leap year compensation up to 2099. ? selectable 12 - hour and 24 - hour modes. ? rtc calibration support. ? oscillator failure detection. ? 32.768 khz crystal oscillator recommends seiko epson fc - 135. when above - mentioned crystal fc - 135 is used, input capacitance (cin) value a nd output capacitance (cout) value recommend 18 pf. when different crystal is used, please set cin and cout capacitance value on enough matching validation. ? 32.768 khz crystal oscillator is affected by pcb pattern, parasitic capacitance, the disturbance. to reduce the above - mentioned influence, please place 32.768 khz crystal connected between xin32k terminal and xout32k terminals and xin32k input capacitance ( cin ) and xout32k output capacitance ( cout ) to the ic as close as possible. in pcb pattern de sign, please be careful about the interference with other signal lines. figure 1 8 . rtc block diagram r t c c l k 3 2 k o u t s n v s c a p 1 u f x o u t 3 2 k x i n 3 2 k v i n l d o _ s n v s 3 . 0 v , 2 5 m a 3 2 . 7 6 8 k h z - x t a l i n t b [ s e i k o e p s o n ; f c - 1 3 5 ] 3 2 k h z o s c c o u t [ 1 8 p f ] c i n [ 1 8 p f ] i n t e r r u p t v o s n v s v d d _ s n v s _ i n ( m a s t e r m o d e ) v d d _ s n v s _ i n ( s l a v e m o d e ) 4 . 7 u f v s y s 25 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (1) oscillation a djustment the oscillation adjustment circuit can be used to correct a time count gain or l oss with high precision by varying the number of 1 - second clock pulses once per 20 or 60 seconds. when dev bit in the trim register is set to "0", oscillation adjustment circuit varies the number of 1 - second clock pulses once per 20 seconds. when dev bit in the trim register is set to "1", oscillation adjustment circuit varies the number of 1 - second clock pulses once per 60 seconds. the oscillation adjustment circuit can be disabled by writing the settings "*,0,0,0,0,0,*" ( "*" represents "0" or "1" ) to t he trim[6:0] in the trim register. conversely, when such oscillation adjustment is to be made, an appropriate oscillation adjustment value can be calculated using the equation below. (a) when o scillation f requency is h igher t han t arget f requency. when se tting dev bit to 0: when setting dev bit to 1: oscillation frequency : frequency of clock pulse output from clk32kout pin. target frequency : desired frequency to be set. generally, a 32.768khz quartz crystal unit has temperature charac teristics that support the highest oscillation frequency at normal temperature. consequently, the quartz crystal unit is recommended to have target frequency settings ranging from 32.768 to 32.76810 khz (+3.05ppm relative to 32.768khz). oscillation adjustm ent value : value that is to be finally written to the trim[6:0] bits in the trim register and is represented in 7 - bit coded decimal notation. (b) when oscillation frequency is equal to target frequency. oscillation adjustment value = 0, +1, - 64, or - 63. (c) when oscillation frequency is lower than target frequency. when setting dev bit to 0: when setting dev bit to 1: oscillation adjustment value calculations are exemplified below ? ? ? ? 1 30 frequency target - frequency n oscillatio 10 1.017 frequency n oscillatio 0.0333 frequency target - frequency n oscillatio value adjustment n oscillatio 6 ? ? ? ? ? ? ? ? ? ? ? ? 10 frequency target - frequency n oscillatio 10 051 . 3 frequency n oscillatio frequency target - frequency n oscillatio value adjustment n oscillatio 6 ? ? ? ? ? ? ? ? ? ? 30 frequency target - frequency n oscillatio 10 017 . 1 frequency n oscillatio frequency target - frequency n oscillatio value adjustment n oscillatio 6 ? ? ? ? ? ? ? ? ? ? 1 10 frequency target - frequency n oscillatio 10 051 . 3 frequency n oscillatio 1 . 0 frequency target - frequency n oscillatio value adjustment n oscillatio 6 ? ? ? ? ? ? ? ? 26 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (ex.a) for an oscillation frequency = 32768.85hz and a ta rget frequency = 32768.05hz when setting dev bit to 0: in this instance, write the settings "00001001" in the trim register. thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h. when setting dev bit to 1: in this instance, write the settings "10011001" in the trim register. (ex.b) for an oscillation frequency = 32762.22hz and a target frequency = 32768.05hz when setting dev bit to 0: to represent an oscillation adjustment valu e of - 58 in 7bit coded decimal notation, subtract 58 (3ah) from 128 (80h) to obtain 46h. in this instance, write the settings of "01000110" in the trim register. thus, an appropriate oscillation adjustment value in the presence of any time count loss repre sents a distance from 80h. when setting dev bit to 1: oscillation adjustment value can be set from - 62 to 63. then, in this case, oscillation adjustment value is out of range. (2) difference b etween dev=0 and dev=1 difference between dev=0 and dev=1 is the following, table 12 . difference b etween dev=0 and dev=1 dev=0 dev=1 maximum value range - 189.2ppm to 189.2ppm - 62ppm to 63ppm minimum resolution 3ppm 1ppm ? ? 25 1 30 05 . 32768 85 . 32768 10 017 . 1 85 . 32768 0333 . 0 05 . 32768 85 . 32768 value adjustment n oscillatio 6 ? ? ? ? ? ? ? ? ? ? ? ? ? 9 1 10 05 . 32768 85 . 32768 10 051 . 3 85 . 32768 1 . 0 05 . 32768 85 . 32768 value adjustment n oscillatio 6 ? ? ? ? ? ? ? ? ? ? ? ? ? 175 30 05 . 32768 22 . 32762 10 017 . 1 22 . 32762 05 . 32768 22 . 32762 value adjustment n oscillatio 6 ? ? ? ? ? ? ? ? ? ? ? ? 58 10 05 . 32768 22 . 32762 10 051 . 3 22 . 32762 05 . 32768 22 . 32762 value adjustment n oscillatio 6 ? ? ? ? ? ? ? ? ? ? 27 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv *1) writing on the min ~ year register is not recommended if the sec register is not also modified. this is because when the seconds digit goes up while accessing i2c, the clock could assume an unpredictable value. this ca n be prevented by writing on the sec register because less than 1hz counter is cleared. (3) typical software - based operations initialization at power - on *1) this step involves ordina ry initialization including the oscillation adjustment register and interrupt cycle settings, etc. writing of time and calendar data start condition *1) write to time counter and calendar counter stop condition start pon=1? yes cpu power on set sec ~ year2 register and trim register and alm*_* register, etc. pon set to 0 no *1) 28 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv *1) when reading clock and calendar counters, do not insert stop condition. *1) this step is intended to disable the alarm interrupt circuit once by clearing alm0_ma sk register in anticipation of the coincidental occurrence of a match between current time and preset alarm time as the alarm interrupt function is set. *2) this step is intended to enable the alarm interrupt function after completion of all alarm interru pt settings. reading time and calendar data alarm0 interrupt process *1) start condition read from time counter and calendar counter stop condition *1) clear alm0_mask register. set alarm threshold registers. (alm0_sec ~ alm0_year) *2) set alm0_mask register. generate interrupt to cpu by irqb check alarm0s bit in status1 register. 1 0 other interrupt processes conduct alarm0 interrupt. (alarm0 interrupt cleared by irq2 address read.) 29 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv 1 2 . i2c bus interface block the i2c compat ible synchronous serial interface provides access to programmable functions and register on the device. this protocol uses a two - wire interface for bi - directional communications between lsis connected to the bus. the two interface lines are serial data line ( sda ), and serial clock line ( scl ). these lines should be connected to the power supply dvdd by a pull - up resistor and remain high even when the bus is idle. (1) start and stop conditions when scl is high, pulling sda low produces a start condition , while pulling sda high produces a stop condition. every instruction is started when a start condition occurs and terminated when a stop condition happens . during read, a stop condition causes read ing to terminate , then the ch ip enters the standby state. during write, a stop condition causes the fetching of write data to terminate, after which writing starts automatically. upon the completion of writing, the chip enters the standby state. two or more start conditions can not b e entered consecutively. figure 19 . start and stop conditions ( 2 ) modifying data data on the sda input can be modified while scl is low. when scl is high, modifying the sda input means a start or stop condit ion. figure 20 . modifying data ( 3 ) acknowledge data is transmitted and received in 8 - bit units. the receiver sends an acknowledge signal by outputting low on sda in the 9th clock cycle, indicating that it has received data normally. the transmitter releases the bus in the 9th clock cycle to receive an acknowledge signal. during write, the chip is always the receiver so that it outputs an acknowledge signal each time it has received eight bits of data. dur ing read, the chip outputs an acknowledge signal after it receives an address following a start condition. then, it outputs read data and releases the bus to wait for an acknowledge signal from the master. when it detects an acknowledge signal, it outputs data at the next address if it does not detect a stop condition. if the chip does not detect an acknowledge signal, it stops read operation and enters the standby state wherein a stop condition occurs subsequently. if the chip does not detect an ack nowledge signal nor a stop condition, it keeps the bus released. figure 21 . acknowledge t s u . d a t t h d . d a t s c l s d a m o d i f y d a t a m o d i f y d a t a t s u . s t a t h d . s t a t s u . s t o s c l s d a s t a r t c o n d i t i o n s t o p c o n d i t i o n s c l s d a 1 8 9 s d a s t a r t c o n d i t i o n a c k n o w l e d g e o u t p u t 30 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv ( 4 ) device addressing after a start condition occurs, a 7 - bit device address and a 1 - bit read/write instruction code are sent as input to the chip . the upper seven bits are called device address, which must always be 1001011. the least significant bit (r/w:read/write) indicates a read instruction when set to 1 and a write instruction when set to 0. an instruction is not e xecuted if the device address does not match the specified value. device address is 1001011. figure 22 . device addressing ( 5 ) write /read operation figure 23 . i2c write / read operation 1 0 0 1 0 1 d e v i c e a d d r e s s c o d e r e a d / w r i t e i n s t r u c t i o n m s b l s b r / w s w a s l a v e a d d r e s s 7 1 s u b a d d r e s s # a 7 0 a w r i t e d a t a ( a ) 7 0 a p s w a s l a v e a d d r e s s 7 1 s u b a d d r e s s # a 7 0 a w r i t e d a t a ( a ) 7 0 a p w r i t e d a t a ( a + 1 ) 7 0 a w r i t e , s i n g l e r e g i s t e r w r i t e , 2 r e g i s t e r s s w a s l a v e a d d r e s s 7 1 s u b a d d r e s s # a 7 0 a w r i t e d a t a ( a ) 7 0 a w r i t e d a t a ( a + 1 ) 7 0 a w r i t e , n - r e g i s t e r s i n c o n t i n u o u s a d d r e s s e s p w r i t e d a t a ( a + n - 1 ) 7 0 a a s w r s r p : s t a r t c o n d i t i o n : w r i t e ( = l ) : r e a d ( = h ) a _ a : s t o p c o n d i t i o n : a c k ( = l ) : n a c k ( = h ) x x : d r i v e d b y m a s t e r : d r i v e d b y s l a v e a s w a s l a v e a d d r e s s 7 1 s u b a d d r e s s # a 7 0 a r e a d , s i n g l e r e g i s t e r s r r a s l a v e a d d r e s s 7 1 _ a r e a d d a t a ( a ) 7 0 p s w a s l a v e a d d r e s s 7 1 s u b a d d r e s s # a 7 0 a r e a d , 2 r e g i s t e r s s r r s l a v e a d d r e s s 7 1 a r e a d d a t a ( a ) 7 0 a _ a r e a d d a t a ( a + 1 ) 7 0 p s w a s l a v e a d d r e s s 7 1 s u b a d d r e s s # a 7 0 a r e a d , n - r e g i s t e r s i n c o n t i n u o u s a d d r e s s e s s r r s l a v e a d d r e s s 7 1 a r e a d d a t a ( a ) 7 0 a _ a r e a d d a t a ( a + n - 1 ) 7 0 p r e a d d a t a ( a + 1 ) 7 0 a a 31 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv ( 6 ) pulling up the sda and scl pins this ic requires sda and scl pins to be pulled up with an external resistor. the values of the pull - up resistors are d etermined by the capacitance of the bus. exceedingly large resist ance combined with a given bus capacitance will result to a rise time that would violate the max imum rise time specification. on the other hand, insufficiently small resis t ance will result in a contention with the pull - down transistor on either slave or master. the recommended pull - up resistance range is 1kohm to 5 kohm. consider the d vdd related input threshold of vih = 0.7 x vdd and vil = 0.3 x vdd for the purposes of rc ti me constant calculation. v(t1) = 0.3 d vdd = d vdd (1 ? e ? t1 / rc ); then t1 = 0.3566749 rc v(t2) = 0.7 d vdd = d vdd (1 ? e ? t2 / rc ); then t2 = 1.2039729 rc t = t2 ? t1 = 0.8473 rc to determine the value of the pull - up resistance, you can cal culate it by using the equation r=t/(0.8473c) t : sda , scl rise time to meet the i2c ac specification. c : total bus capacitance on each sda , scl line . ( 7 ) about limitation of i2c write data is synchronized with internal clock. if internal fifo is full, not generating an acknowledge for write data. for example, continuous addressing access with more than 294khz in i2c. 1 3 . interrupt handling t he system is informed about important events through interrupts. enabled interrupt events are signaled to the processor by driving the intb pin low. each interrupt can be disabled by setting the corresponding enable bit to 0 . each interrupt is l atched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. each interrupt can be cleared by writing 1 to the appropriate bit in the interrupt status register; this will also cause the intb pin to go high. if there are multiple interrupt bits , the intb pin will remain low until all are cleared. if a new interrupt occurs while the processor clears an existing interrupt bit, the intb pin will remain low. the ic powers up with all interrupts disabled , so t he processor must initially poll the device to determine if any interrupts are active. alternatively, the processor can enable the interrupt bits of interest. interrupts generated by external events are debounced; therefore, the event needs to be stable th roughout the debounce period before an interrupt is generated. nominal debounce periods for each event are documented in the i nterrupt summary. due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly. table 13 . interrupt summary address bit address bit address bit address bit buck4fault 88 3 95 3 1khz vbat_ov_det 8e 7 9b 7 128hz buck3fault 88 2 95 2 1khz vbat_ov_res 8e 6 9b 6 128hz buck2fault 88 1 95 1 1khz vbat_lo_det 8e 5 9b 5 128hz buck1fault 88 0 95 0 1khz vbat_lo_res 8e 4 9b 4 128hz dcin_ov_det 89 5 96 5 1khz vbat_sht_det 8e 3 9b 3 128hz dcin_ov_res 89 4 96 4 1khz vbat_sht_res 8e 2 9b 2 128hz dcin_clps_in 89 3 96 3 4khz dbat_det 8e 1 9b 1 128hz dcin_clps_out 89 2 96 2 4khz vbat_mon_det 8f 1 9c 1 128hz dcin_rmv 89 1 96 1 1khz vbat_mon_res 8f 0 9c 0 128hz dcin_mon_det 8a 1 97 1 4khz batcap_mon3_det 90 2 9d 2 1hz dcin_mon_res 8a 0 97 0 4khz batcap_mon2_det 90 1 9d 1 1hz vsys_mon_det 8b 7 98 7 128hz batcap_mon1_det 90 0 9d 0 1hz vsys_mon_res 8b 6 98 6 128hz ocur3_det 91 5 9e 5 4khz vsys_lo_det 8b 3 98 3 128hz ocur3_res 91 4 9e 4 4khz vsys_lo_res 8b 2 98 2 128hz ocur2_det 91 3 9e 3 4khz vsys_uv_det 8b 1 98 1 128hz ocur2_res 91 2 9e 2 4khz vsys_uv_res 8b 0 98 0 128hz ocur1_det 91 1 9e 1 4khz chg_trns 8c 7 99 7 32.768khz ocur1_res 91 0 9e 0 4khz tmp_trns 8c 6 99 6 32.768khz vf_mon_det 92 7 9f 7 1hz bat_mnt_in 8c 5 99 5 1khz vf_mon_res 92 6 9f 6 1hz bat_mnt_out 8c 4 99 4 1khz vf_f125_det 92 5 9f 5 128hz chg_wdt_exp 8c 3 99 3 32.768khz vf_f125_res 92 4 9f 4 128hz extemp_tout 8c 2 99 2 32.768khz ovbtmp_det 92 3 9f 3 1hz th_det 8d 7 9a 7 1hz ovbtmp_res 92 2 9f 2 1hz th_rmv 8d 6 9a 6 1hz lobtmp_det 92 1 9f 1 1hz bat_det 8d 5 9a 5 128hz lobtmp_res 92 0 9f 0 1hz bat_rmv 8d 4 9a 4 128hz alm2 93 2 a0 2 128hz tmp_out_det 8d 1 9a 1 1hz alm1 93 1 a0 1 128hz tmp_out_res 8d 0 9a 0 1hz alm0 93 0 a0 0 128hz debounce interval [hz] (3 times match) enable status/clear interrupt event debounce interval [hz] (3 times match) register map enable status/clear interrupt event register map 32 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv absolute maximum ratings ( ta=25c) parameter symbol rating unit maximum supply voltage 1 dcin v dcin max 30 v maximum supply voltage 2 vin, pvin1,2,3,4, vinl1, vinl2 v in max p vin max v inl1 max v inl2 max 6 .0 v maximum supply voltage 3 dvdd v dvdd max 4.5 v power dissipation (note1 ) pd 4 . 16 w operating temperature range topr - 40 to +85 c storage temperature range tstg - 55 to +125 c (note 1) derate by 4 1 . 6mw/c when operating above ta=25c ( when mount ed in rohms standard board 74.2x74.2 x1.6tmm ). caution: operating the ic over the absolute maximum ratings may damage the ic. the damage can either be a short circuit between pins o r an open circuit between pins and the internal circuitry. therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the ic is operated over the absolute maximum ratings. recommended operating conditions parameter symbol limits unit input voltage range 1 dcin v dcin 3.5 to 28 v input voltage range 2 (note2) vin, pvin1,2,3,4 v in p vin 3.3 to 5.5 v input voltage range 3 vinl1, vinl2 v inl1 v inl2 2.6 to 5.5 v input voltage range 4 dvdd v dvdd 1.5 to 3.4 v (note2) i t is necessary to supply the same voltage to v in , and pv in 1,2,3,4 33 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv electrical characteristics ( unless otherwise specified, ta= + 25 ? c , v in= p vin = 4.0 v, dvdd= 1.8 v, buck1=1.425 v , buck2=1.2v, buck3 = vinl1=vinl2=3.3v, buck4=1.8v, ldo1=1.2v, ldo2=ldo3=3.3v 34 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv ( unless otherwise specified, ta= + 25 ? c , v in= p vin = 4.0 v, dvdd= 1.8 v, buck1=1.425 v , buck2=1.2v, buck3 = vinl1=vinl2=3.3v, buck4=1.8v, ldo1=1.2v, ldo2=ldo3=3.3v 35 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (unless otherwise specified, ta= + 25 ? buck3 C high, nvcc33_io, wifi, emmc, others output voltage v osw3 3.250 3.300 3.350 v initial value , io=200ma pwm mode programmable output voltage range v orsw3 2.60 - 3.350 v 50mv step output current i osw3 - - 1 000 ma pwm mode load stability l sw3 - 10 20 mv io= 1ma to 1 00 0ma , pwm mode efficiency sw31 - 9 2 - % vo=3.3v, io= 1 ma inductor rdc=84m sw32 - 9 5 - % vo=3.3v, io=200ma indu ctor rdc=84m sw3 - 2.5 - mhz vo = 3.3v , io=200ma pwm mode turn - on time t onsw3 - - 500 usec discharge resistance r dissw3 - 600 - buck3 1.5 2.2 - buck3 4.7 10 - buck4 C nvcc18_io, lpddr(1.8v), others output voltage v osw4 1.773 1.800 1.827 v initial value , io=200ma pwm mode programmable output voltage range v orsw4 1.0 0 - 2.70 v 50mv step output current i osw4 - - 1000 ma pwm mode load stability l sw4 - 10 20 mv io= 1ma to 100 0ma , pwm mode efficiency sw41 - 8 6 - % vo=1.8v , io = 1ma inductor rdc=84m sw42 - 90 - % vo=1.8v , io=200ma inductor rdc=84m sw4 - 2.5 - mhz vo = 1.8v , io=200ma pwm mode turn - on time t onsw4 - - 500 usec discharge resistance r dissw4 - 600 - sw 4 1.5 2.2 - sw 4 4.7 10 - 36 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv ( unless otherwise specified, ta= + 25 ? ldo1 output voltage v ol1 1. 176 1.200 1.2 24 v initial value io= 50 ma programmable output voltage range v orl1 0.80 - 3.30 v 50mv step output current i ol1 - - 300 ma dropout voltage v o dp l 1 - 0.10 - v io=5 0 ma vi nl1=3.2v (vo=3.3v setting) input voltage stability il 1 - 2 5 mv vin =pvin= 3.5 v to 4.5v, io=50ma load stability ll 1 - 10 20 mv io= 1ma to 1 50ma discharge resistance r disl1 - 600 - l 1 - 60 - db vin=pvin=4.2v, vr= 0.4 v pp , fr= 120 hz , io= 5 ma, vo= 1.2 v bw=20hz to 20khz output capacitor c o l1 0.47 1.0 - f ? ldo2 output voltage v ol2 3. 234 3.300 3. 366 v initial value io= 50 ma programmable output voltage range v orl2 0.80 - 3.30 v 50mv step output current i ol2 - - 300 ma dropout voltage v o dp l 2 - 0.10 - v io=5 0 ma vinl2=3.2v (vo=3.3v setting) input voltage stability il 2 - 2 5 mv vi n =pvin= 3.5 v to 4.5v, io=50ma load stability ll 2 - 10 20 mv io= 1ma to 1 50ma discharge resist ance r disl2 - 600 - l 2 - 60 - db vin= pvin=4.2v, vr= 0.4vpp , fr= 120 hz , io= 5 ma, vo= 3.3 v bw=20hz to 20khz output capacitor c o l2 0.47 1.0 - f ? 37 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (unless otherwise specified, ta= + 25 ? ldo3 output voltage v ol3 3. 234 3.300 3. 366 v initial value io= 50 ma programmable output voltage range v orl 3 0.80 - 3.30 v 50mv step output current i ol3 - - 300 ma dropout voltage v o dp l 3 - 0.10 - v io=5 0 ma vinl2=3.2v (vo=3.3v setting) input voltage stability il 3 - 2 5 mv vin= pvin= 3.5 v to 4.5v, io=50ma load stability ll 3 - 10 20 mv io= 1ma to 1 50ma d ischarge resistance r d isl 3 - 600 - l 3 - 60 - db v in = p vin =4.2v, vr= 0.4vpp , fr= 120 hz , i o= 5 ma, vo= 3.3. v bw=20hz to 20khz output capacitor c ol3 0.47 1.0 - f ? ldo_dvref (ddr_vref) output voltage v ol4 dvrefin *0.49 dvrefin *0.50 dvrefin *0.51 v io= 5ma output current i ol4 - - 10 ma input voltage stability il 4 - 2 5 mv v in = p vin = 3.5 v to 4.5v, io= 5ma load stability ll 4 - 10 20 mv io= 1ma to 10m a discharge resistance r disl4 - 600 - o l4 0.47 1.0 - f ? ldo_snvs output voltage v ol5 2.94 3.00 3.06 v io= 10 ma output current i ol5 - - 25 ma input voltage stability il 5 - 2 5 mv v in = p vin = 3.5 v to 4.5v, io= 1 0ma load stabil ity ll 5 - 10 20 mv io= 1ma to 1 0ma output capacitor c o l5 0.47 1.0 - f ? 38 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (unless otherwise specified, ta= + 25 ? li - ion battery charger C ovp dcin uvlo release voltage v dc in _ uvlo 3.7 3.8 3. 9 v dcin rising dcin uvlo hysteresis range v dc in _ uvlo hys 100 1 5 0 200 mv dcin ovp detection voltage v dcin _ ovp 6.3 6.5 6.7 v dcin rising dcin ovp hysteresis range v dcin _ ovp hys 100 150 200 mv voltage output turn - on time t dcin _on - 5 10 msec dcin input current in ovp state i dcin _ovp - - 3 ma dcin < 28v li - ion battery charger fast charging current range i batchg_ r 100 - 2000 ma 100ma step fast charging current accuracy i batchg_ a c - 1 0 - % ichg=500ma pre charging current range i batpre_ r 100 - 5 00 ma tric k le charging current range i tri _ r 20 - 100 ma 10ma step pre charging detection voltage low v pre_l 2.1 - 3.6 v bat rising, 100mv step pre charg ing detection voltage high v pre_h 2.1 - 3.6 v bat rising, 100mv step battery charging voltage range v chg_r 3.72 - 4.3 4 v bat ovp detection v bovp 4.4 - 4.8 v 50mv step charging termination current range i chg_term 1 0 - 2 00 ma 50ma step charging termination current accuracy i chg_term _ ac - 2 0 - % ichg_term= 5 0ma setting enter supplement mode voltage threshold v bs 20 60 100 mv vbat - vsys voltage exit supplement mode voltage threshold v bsth - 40 - mv on - state resistance between system and vbat r on_vbat 4 0 80 1 60 m pre 11 6 12 9 14 2 min battery error detection time ( fast c harging time ) t fast 57 7 64 1 70 5 min b attery error detection time ( high temperature protection ) t htpro 1 16 12 9 1 4 2 min over 58c charging termination delay time t topoff 13 15 17 sec chgled output toggling frequency f chgled 0.48 0.6 0.72 hz at temp error1 or 2 battery high volta ge threshold v bat _ h 3.0 - 3.6 v for vbat rising detection battery low voltage threshold v bat _ l 2.5 - 3.1 v for vbat falling detection battery short - circuit detection voltage v bat _ sht 1.4 1.5 1.6 v battery short - circuit detectio n hysteresis range v bat _ sht hys - 0.1 - v battery detection load current i bat_det - 20 - ma battery temperature threshold hot t btmp _hot - 58 - c 39 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (unless otherwise specified, ta= + 25 ? li - ion battery charger (continued) battery temperature threshold cold t btmp _cold - 2 - c battery temperature measurement accuracy t bat - 3 - 3 c t s threshold disable voltage v t s _d is 0.06 0.1 0.17 v battery open detection voltage v ts _batop n 1.25 1.39 1.53 v measure ts voltage coulomb counter resolution res cc - - 15 bit sign + 14 - bits operating clock frequency f c c - 32.768 - khz xtal integration period t conv cc - 1 - s ec analog input voltage range v ain ? v ain ? dco - 0.5 - +0.5 mv linearity l in - 4 - lsb v ain r ange 12 - bit sar adc resolution res sar - - 12 bit operating clock frequency f sar - 400 - khz conversion period t conv sar - 40 - s ain1 0.6 - 5. 4 v vbat input analog input voltage range 2 v ain2 0.2 - 1. 3 v ts input analog input voltage range 3 v ain 3 - 30 - 30 mv battp input differential non - linearity dnl - 3 - lsb ts input integral non - linearity inl - 6 - lsb ts inpu t rtc / output buffer (clk32kout) clock frequency f rt c - 32.768 - khz with external crystal output clock frequency drift d rtc c lk ? rtcs tb - - 1000 msec within 3% of target frequency. oscillator stop detection t stpdet - - 150 sec rtc - 3 - a l =20pf output duty cycle duty rtc 30 50 70 % output l level voltage v ol32k - - 0.4 v i ol = 1ma output off leak current i off32k - - 1 a clk32kout =5.5v,vin=5.5v open drain o utput off mode (note1) frequency stability over temperature depends on the characteristics of the crystal unit which is expressed as a quadr atic function. recommended crystal unit is fc - 135( seiko epson ). 40 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv (unless otherwise specified, ta= + 25 ? i2c bus interface i2c_clk clock frequency f scl 0 - 4 00 k hz hold time start condition t hd;sta 160 - - nsec low period o f i2c_clk clock t low 160 - - n sec high period of i2c_clk clock t high 60 - - nsec set - up time for a repeated start condition t su;sta 160 - - nsec data hold time t hd;dat 0 - 70 nsec data set - up time t su;dat 10 - - nsec set - up time for stop conditio n t su;sto 160 - - nsec capacitive load for each bus line c b - - 100 pf pulse width of spikes that are suppressed by the input filter * t sp 0 - 10 ns bus free time t buff 1.3 - - us figure 2 4 . i2c ac timing figure 25 . i2c ac timing C bus free time s c l s d a t b u f f t s u : s t o p s s c l s d a t s u ; d a t t r d a 3 0 % 7 0 % 3 0 % 7 0 % t l o w t h i g h t h d ; d a t t r c l 1 t f c l t r c l t l o w t h i g h t s u ; s t o t r c l 1 s r p s r t s u ; s t a t h d ; s t a 41 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv register map adrs. register name r/w init mst init slv d7 d6 d5 d4 d3 d2 d1 d0 00h device r, r/w 41h 41h i2c_unempty 01h pwrctrl r/w 00h 00h - stby_inv - - - restarten 02h buck1_on r/w 19h 17h - - 03h buck1_stby r/w 19h 17h - - 04h buck1_slp r/w 19h 17h - - 05h buck1_mode r/w 06h 06h - - buck1_omode - 06h buck1_conf r/w 00h 00h - - - - - - 07h buck2_on r/w 10h 17h - - 08h buck2_stby r/w 10h 17h - - 09h buck2_slp r/w 10h 17h - - 0ah buck2_mode r/w 06h 06h - - buck2_omode - 0bh buck2_conf r/w 00h 00h - - - - - - 0ch buck3_volt r/w 0eh 0bh - - - - 0dh buck3_mode r/w 06h 06h - - buck3_omode - 0eh buck4_volt r/w 10h 04h - - - 0fh buck4_mode r/w 06h 06h - - buck4_omode - 10h ldo1_ctrl r/w 11h 0fh - - - vosnvs_sw_en dvref_en ldo3_en ldo2_en ldo1_en 11h ldo2_ctrl r/w 00h 00h - - ldo3_lpwr ldo3_stby ldo2_lpwr ldo2_stby ldo1_lpwr ldo1_stby 12h ldo1_volt r/w 08h 22h - - 13h ldo2_volt r/w 32h 14h - - 14h ldo3_volt r/w 32h 08h - - 15h buck_pden r/w 0fh 0fh - - - - buck4_pden buck3_pden buck2_pden buck1_pden 16h ldo_pden r/w 0fh 0fh - - - - dvref_pden ldo3_pden ldo2_pden ldo1_pden 17h gpo r/w 07h 07h - gpo3_mode gpo2_mode gpo1_mode - gpo3_out gpo2_out gpo1_out 18h out32k r/w 01h 01h - - - - - - out32k_mode out32k_en 19h sec r/w xxh xxh - s40 s20 s10 s8 s4 s2 s1 1ah min r/w xxh xxh - m40 m20 m10 m8 m4 m2 m1 1bh hour r/w xxh xxh 12/24 - h20/pa h10 h8 h4 h2 h1 1ch week r/w 0xh 0xh - - - - - w4 w2 w1 1dh day r/w xxh xxh - - d20 d10 d8 d4 d2 d1 1eh month r/w xxh xxh - - - mo10 mo8 mo4 mo2 mo1 1fh year r/w xxh xxh y80 y40 y20 y10 y8 y4 y2 y1 20h alm0_sec r/w 00h 00h - a0s40 a0s20 a0s10 a0s8 a0s4 a0s2 a0s1 21h alm0_min r/w 00h 00h - a0m40 a0m20 a0m10 a0m8 a0m4 a0m2 a0m1 22h alm0_hour r/w 00h 00h a0_12/24 - a0h20/pa a0h10 a0h8 a0h4 a0h2 a0h1 23h alm0_week r/w 00h 00h - - - - - a0w4 a0w2 a0w1 24h alm0_day r/w 00h 00h - - a0d20 a0d10 a0d8 a0d4 a0d2 a0d1 25h alm0_month r/w 00h 00h - - - a0mo10 a0mo8 a0mo4 a0mo2 a0mo1 26h alm0_year r/w 00h 00h a0y80 a0y40 a0y20 a0y10 a0y8 a0y4 a0y2 a0y1 27h alm1_sec r/w 00h 00h - a1s40 a1s20 a1s10 a1s8 a1s4 a1s2 a1s1 28h alm1_min r/w 00h 00h - a1m40 a1m20 a1m10 a1m8 a1m4 a1m2 a1m1 buck1_slp[5:0] ldo1[5:0] ldo2[5:0] ldo3[5:0] buck2_slp[5:0] buck2_stby[5:0] buck2_on[5:0] buck1_ramprate[1:0] buck1_onstbymode[3:0] lsiver [2:0] deviceid[3:0] pwron_dbnc[1:0] buck1_on[5:0] buck1_stby[5:0] buck3_onstbymode[3:0] buck4_onstbymode[3:0] buck4_on[4:0] buck3_on[3:0] buck2_ramprate[1:0] buck2_onstbymode[3:0] 42 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv register map - continued adrs. register name r/w init mst init slv d7 d6 d5 d4 d3 d2 d1 d0 29h alm1_hour r/w 00h 00h a1_12/24 - a1h20/pa a1h10 a1h8 a1h4 a1h2 a1h1 2ah alm1_week r/w 00h 00h - - - - - a1w4 a1w2 a1w1 2bh alm1_day r/w 00h 00h - - a1d20 a1d10 a1d8 a1d4 a1d2 a1d1 2ch alm1_month r/w 00h 00h - - - a1mo10 a1mo8 a1mo4 a1mo2 a1mo1 2dh alm1_year r/w 00h 00h a1y80 a1y40 a1y20 a1y10 a1y8 a1y4 a1y2 a1y1 2eh alm0_mask r/w 00h 00h a0_onesec a0_year a0_mon a0_day a0_week a0_hour a0_min a0_sec 2fh alm1_mask r/w 00h 00h a1_onesec a1_year a1_mon a1_day a1_week a1_hour a1_min a1_sec 30h alm2 r/w 00h 00h - - - - - - alm2[1:0] 31h trim r/w 00h 00h dev 32h conf r/w 01h 01h - - - - - - xstb pon 33h sys_init r/w 00h 00h - - - - - - chgrst - 34h chg_state r xxh xxh - 35h chg_last_state r xxh xxh - 36h bat_stat r xxh xxh - - bat_det bat_det_done vbat_ov low_bat vbat_short dbat_det 37h dcin_stat r 0xh 0xh - - - - dcin_ov inhibit (note1) dcin_clps dcin_det 38h vsys_stat r 0xh 0xh - - - - - - vsys_lo vsys_uvn 39h chg_stat r 0xh 0xh - - - - - - - vrechg_det 3ah chg_wdt_stat r xxh xxh 3bh bat_temp r 0xh 0xh - - - - - 3eh dcin_clps r/w 36h 36h 3fh vsys_reg r/w 09h 09h - - - inhibit (note1) 40h vsys_max r/w 23h 21h - 41h vsys_min r/w 21h 1fh - 42h chg_set1 r/w 6fh 6fh wdt_dis wdt_auto auto_fst fst_trg auto_rechg btmp_en cold_err_en chg_en 43h chg_set2 r/w 90h 90h vf_treg_en - rebatdet batdet_en - - 44h chg_wdt_pre r/w 1eh 1eh 45h chg_wdt_fst r/w 26h 26h 46h chg_ipre r/w 52h 52h 47h chg_ifst r/w 04h 04h - - - 48h chg_ifst_term r/w 05h 05h - - - - 49h chg_vpre r/w c9h c9h 4ah chg_vbat_1 r/w 18h 18h - - - 4bh chg_vbat_2 r/w 13h 13h - - - 4ch chg_vbat_3 r/w 10h 10h - - - 4dh chg_led_1 r/w 03h 03h - - - - - 4eh vf_th r/w 00h 00h 4fh bat_set_1 r/w 00h 00h 50h bat_set_2 r/w 30h 30h - 51h bat_set_3 r/w 02h 02h - - - - - tim_dbp[2:0] (note1) please always write "0" to the inhibit register when in use. terr[2:0] vf_th[7:0] vbat_hi[3:0] vbat_lo[3:0] vbat_ovp[3:0] vbat_mnt[2:0] ifst_term[3:0] vpre_hi[3:0] vpre_lo[3:0] vbat_chg1[4:0] vbat_chg2[4:0] vbat_chg3[4:0] tim_cnt_sel[1:0] wdt_pre[7:0] wdt_fst[7:0] itri[3:0] ipre[3:0] ifst[4:0] bat_temp[2:0] dcin_clps[7:0] vsys_reg[3:0] vsys_max[6:0] vsys_min[6:0] trim[6:0] chg_state[6:0] chg_last_state[6:0] chgwdts[7:0] 43 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv register map - continued adrs. register name r/w init mst init slv d7 d6 d5 d4 d3 d2 d1 d0 52h alm_vbat_th_u r/w 01h 01h - - - - - - - vbat_th[8] 53h alm_vbat_th_l r/w ffh ffh 54h alm_dcin_th r/w 0fh 0fh 55h alm_vsys_th r/w ffh ffh 56h vm_ibat_u r 00h 00h - - - - 57h vm_ibat_l r 00h 00h 58h vm_vbat_u r 00h 00h - - - 59h vm_vbat_l r 00h 00h 5ah vm_btmp r/w 00h 00h 5bh vm_vth r/w 00h 00h 5ch vm_dcin_u r 00h 00h - - - - 5dh vm_dcin_l r 00h 00h 5eh vm_vsys r 00h 00h 5fh vm_vf r 00h 00h 60h vm_ibatload_pre_u r 00h 00h - - - - 61h vm_ibatload_pre_l r 00h 00h 62h vm_vbatload_pre_u r 00h 00h - - - 63h vm_vbatload_pre_l r 00h 00h 64h vm_ibatload_pst_u r 00h 00h - - - - 65h vm_ibatload_pst_l r 00h 00h 66h vm_vbatload_pst_u r 00h 00h - - - 67h vm_vbatload_pst_l r 00h 00h 68h vm_sma_vbat_u r 00h 00h - - - 69h vm_sma_vbat_l r 00h 00h 6ah vm_sma_ibat_u r 00h 00h - - - - 6bh vm_sma_ibat_l r 00h 00h 6dh cc_ctrl r/w 40h 40h ccntrst ccntenb cc_calib - - - - - 6eh cc_batcap1_th_u r/w 00h 00h - - - - 6fh cc_batcap1_th_l r/w 7eh 7eh 70h cc_batcap2_th_u r/w 00h 00h - - - - 71h cc_batcap2_th_l r/w 3fh 3fh 72h cc_batcap3_th_u r/w 00h 00h - - - - 73h cc_batcap3_th_l r/w 1fh 1fh 74h cc_stat r 00h 00h - - - - - cc_mon3 cc_mon2 cc_mon1 75h cc_ccntd_3 r/w 0xh 00h - - - - 76h cc_ccntd_2 r/w xxh 00h 77h cc_ccntd_1 r/w xxh 00h 78h cc_ccntd_0 r/w xxh 00h 79h cc_curcd_u r xxh 00h curdir - 7ah cc_curcd_l r xxh 00h ccntd[7:0] curcd[13:8] curcd[7:0] cc_batcap2_th[7:0] cc_batcap3_th[11:8] cc_batcap3_th[7:0] ccntd[27:24] ccntd[23:16] ccntd[15:8] vbat_sma[7:0] ibat_sma[11:8] ibat_sma[7:0] cc_batcap1_th[11:8] cc_batcap1_th[7:0] cc_batcap2_th[11:8] vbat_batload_pre[7:0] ibat_batload_pst[11:8] ibat_batload_pst[7:0] vbat_batload_pst[12:8] vbat_batload_pst[7:0] vbat_sma[12:8] dcin[7:0] vsys[7:0] vf[7:0] ibat_batload_pre[11:8] ibat_batload_pre[7:0] vbat_batload_pre[12:8] ibat[7:0] vbat[12:8] vbat[7:0] btmp[7:0] vth[7:0] dcin[11:8] vbat_th[7:0] dcin_th[7:0] vsys_th[7:0] ibat[11:8] 44 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv register map - continued adrs. register name r/w init mst init slv d7 d6 d5 d4 d3 d2 d1 d0 7bh vm_ocur_thr_1 r/w 7dh 7dh 7ch vm_ocur_dur_1 r/w 64h 64h 7dh vm_ocur_thr_2 r/w 5eh 5eh 7eh vm_ocur_dur_2 r/w 8ch 8ch 7fh vm_ocur_thr_3 r/w 4eh 4eh 80h vm_ocur_dur_3 r/w a5h a5h 81h vm_ocur_mon r 0xh 00h - - - - - ocur3 ocur2 ocur1 82h vm_btmp_ov_thr r/w 8ch 8ch 83h vm_btmp_ov_dur r/w 28h 28h 84h vm_btmp_lo_thr r/w c8h c8h 85h vm_btmp_lo_dur r/w 28h 28h 86h vm_btmp_mon r 0xh 00h - - - - - - ovbtmp lobtmp 88h int_en_01 r/w 00h 00h - - - - buck4fault buck3fault buck2fault buck1fault 89h int_en_02 r/w 00h 00h - - dcin_ov_det dcin_ov_res dcin_clps_in dcin_clps_out dcin_rmv - 8ah int_en_03 r/w 00h 00h - - - - - - dcin_mon_det dcin_mon_res 8bh int_en_04 r/w 08h 00h vsys_mon_det vsys_mon_res - - vsys_lo_det vsys_lo_res vsys_uv_det vsys_uv_res 8ch int_en_05 r/w 00h 00h chg_trns tmp_trns bat_mnt_in bat_mnt_out chg_wdt_exp extemp_tout - - 8dh int_en_06 r/w 00h 00h th_det th_rmv bat_det bat_rmv - - tmp_out_det tmp_out_res 8eh int_en_07 r/w 00h 00h vbat_ov_det vbat_ov_res vbat_lo_det vbat_lo_res vbat_sht_det vbat_sht_res dbat_det - 8fh int_en_08 r/w 00h 00h - - - - - - vbat_mon_det vbat_mon_res 90h int_en_09 r/w 00h 00h - - - - - cc8th_det cc4th_det cc2nd_det 91h int_en_10 r/w 00h 00h - - ocur3_det ocur3_res ocur2_det ocur2_res ocur1_det ocur1_res 92h int_en_11 r/w 00h 00h vf_det vf_res vf125_det vf125_res ovtmp_det ovtmp_res lotmp_det lotmp_res 93h int_en_12 r/w 00h 00h - - - - - alm2 alm1 alm0 94h int_stat r 00h 00h buck_ast dcin_ast vsys_ast chg_ast bat_ast bmon_ast tmp_ast alm_ast 95h int_stat_01 r/wc 00h 00h - - - - buck4fault buck3fault buck2fault buck1fault 96h int_stat_02 r/wc 00h 00h - - dcin_ov_det dcin_ov_res dcin_clps_in dcin_clps_out dcin_rmv - 97h int_stat_03 r/wc 00h 00h - - - - - - dcin_mon_det dcin_mon_res 98h int_stat_04 r/wc 00h 00h vsys_mon_det vsys_mon_res - - vsys_lo_det vsys_lo_res vsys_uvdet vsys_uv_res 99h int_stat_05 r/wc 00h 00h chg_trns tmp_trns bat_mnt_in bat_mnt_out chg_wdt_exp extemp_tout - - 9ah int_stat_06 r/wc 00h 00h th_det th_rmv bat_det bat_rmv - - tmp_out_det tmp_out_res 9bh int_stat_07 r/wc 00h 00h vbat_ov_det vbat_ov_res vbat_lo_det vbat_lo_res vbat_sht_det vbat_sht_res dbat_det - 9ch int_stat_08 r/wc 00h 00h - - - - - - vbat_mon_det vbat_mon_res 9dh int_stat_09 r/wc 00h 00h - - - - - cc8th_det cc4th_det cc2nd_det 9eh int_stat_10 r/wc 00h 00h - - ocur3_det ocur3_res ocur2_det ocur2_res ocur1_det ocur1_res 9fh int_stat_11 r/wc 00h 00h vf_det vf_res vf125_det vf125_res ovtmp_det ovtmp_res lotmp_det lotmp_res a0h int_stat_12 r/wc 00h 00h - - - - - alm2 alm1 alm0 a1h int_update r/wc 00h 00h - - - - - - - int_update a2h- ffh - - 00h 00h - - - - - - - - ocurthr1[7:0] ocurdur1[7:0] ocurthr2[7:0] lobtmpdur[7:0] ocurdur2[7:0] ocurthr3[7:0] ocurdur3[7:0] ovbtmpthr[7:0] ovbtmpdur[7:0] lobtmpthr[7:0] 45 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 04h: buck1_slp register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck1_slp r/w - - initial value (master mode) 19h 0 0 0 1 1 0 0 1 initial value (slave mode) 17h 0 0 0 1 0 1 1 1 bit 5-0 : buck1_slp[5:0] sets the buck1 output voltage during "sleep" mode. see table 5 and table 6 for all possible configurations. 04h buck1_slp[5:0] address 02h: buck1_on register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck1_on r/w - - initial value (master mode) 19h 0 0 0 1 1 0 0 1 initial value (slave mode) 17h 0 0 0 1 0 1 1 1 bit 5-0 : buck1_on[5:0] sets the buck1 output voltage during "on" mode. see table 5 and table 6 for all possible configurations. 02h buck1_on[5:0] address 03h: buck1_stby register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck1_stby r/w - - initial value (master mode) 19h 0 0 0 1 1 0 0 1 initial value (slave mode) 17h 0 0 0 1 0 1 1 1 bit 5-0 : buck1_stby[5:0] sets the buck1 output voltage during "standby" mode. see table 5 and table 6 for all possible configurations. 03h buck1_stby[5:0] address 00h: device register (r, r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 device r, r/w i2c_unempty initial value (master mode) 41h 0 1 0 0 0 0 0 1 initial value (slave mode) 41h 0 1 0 0 0 0 0 1 bit 7 : i2c_unempty 0 : the buffer passed to rtc from i2c is empty. 1 : the buffer passed to rtc from i2c is not empty. bit 7-4 : lsiver [3:0] lsi version bit 3-0 : device id[3:0] device id 00h lsiver [2:0] deviceid[3:0] address 01h: pwrctrl register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pwrctrl r/w - stby_inv - - - restarten initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 6 : stby_inv standby pin polarity setting 0 : standby pin high active 1 : standby pin low active bit 3-2 : pwron_dbnc[1:0] pwron hardware debounce time setting pwron_dbnc [1:0] turn on debounce (ms) 00 0 01 31.25 10 125 11 750 bit 0 : restarten restart the ic 0 : normal 1 : restart the ic 01h pwron_dbnc[1:0] 46 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv buck1 onstbymode[3:0] on mode standby mode 0000 off off 0001 pwm off 0010 reserved reserved 0011 pfm off 0100 pfm/pwm auto off 0101 pwm pwm 0110 pwm pfm/pwm auto 0111 reserved reserved 1000 pfm/pwm auto pfm/pwm auto 1001 reserved reserved 1010 reserved reserved 1011 reserved reserved 1100 pfm/pwm auto pfm 1101 pwm pfm 1110 reserved reserved 1111 reserved reserved buck mode control description mode description off buck is switched off and the output voltage is discharged. pfm buck is always in pfm mode, which is useful at light loads for optimized efficiency. pwm buck is always in pwm mode operation regardless of load conditions. pwm/pwm auto buck moves automatically between pfm mode and pwm mode depending on load conditions. address 05h: buck1_mode register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck1_mode r/w - - buck1_omode - initial value (master mode) 06h 0 0 0 0 0 1 1 0 initial value (slave mode) 06h 0 0 0 0 0 1 1 0 bit 5 : buck1_omode buck1 operational mode control when "pwron = h l" (slave mode only) 0 : off 1 : sleep mode bit 3-0 : buck1_onstbymode[3:0] buck1 operational mode control when in "on, standby" mode 05h buck1_onstbymode[3:0] address 06h: buck1_conf register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck1_conf r/w - - - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 1-0 : buck1_ramprate[1:0] buck1 dvs ramp rate setting 00 : 10.0mv/usec 01 : 5.0mv/usec 10 : 2.5mv/usec 11 : 1.25mv/usec 06h buck1_ramprate[1:0] address 07h: buck2_on register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck2_on r/w - - initial value (master mode) 10h 0 0 0 1 0 0 0 0 initial value (slave mode) 17h 0 0 0 1 0 1 1 1 bit 5-0 : buck2_on[5:0] sets the buck2 output voltage during "on" mode. see table 5 and table 6 for all possible configurations. 07h buck2_on[5:0] address 08h: buck2_stby register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck2_stby r/w - - initial value (master mode) 10h 0 0 0 1 0 0 0 0 initial value (slave mode) 17h 0 0 0 1 0 1 1 1 bit 5-0 : buck2_stby[5:0] sets the buck2 output voltage during "standby" mode. see table 5 and table 6 for all possible configurations. 08h buck2_stby[5:0] 47 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 09h: buck2_slp register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck2_slp r/w - - initial value (master mode) 10h 0 0 0 1 0 0 0 0 initial value (slave mode) 17h 0 0 0 1 0 1 1 1 bit 5-0 : buck2_slp[5:0] sets the buck2 output voltage during "sleep" mode. see table 5 and table 6 for all possible configurations. 09h buck2_slp[5:0] address 0ah: buck2_mode register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck2_mode r/w - - buck2_omode - initial value (master mode) 06h 0 0 0 0 0 1 1 0 initial value (slave mode) 06h 0 0 0 0 0 1 1 0 bit 5 : buck2_omode buck2 operational mode control when "pwron = h l"(slave mode only) 0 : off mode 1 : sleep mode bit 3-0 : buck2_onstbymode[3:0] buck2 operational mode control when in "on, standby" mode 0ah buck2_onstbymode[3:0] address 0bh: buck2_conf register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck2_conf r/w - - - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 1-0 : buck2_ramprate[1:0] buck2 dvs ramp rate setting 00 : 10.0mv/usec 01 : 5.0mv/usec 10 : 2.5mv/usec 11 : 1.25mv/usec 0bh buck2_ramprate[1:0] address 0ch: buck3_volt register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck3_volt r/w - - - - initial value (master mode) 0eh 0 0 0 0 1 1 1 0 initial value (slave mode) 0bh 0 0 0 0 1 0 1 1 bit 3-0 : buck3_on[3:0] sets the buck3 output voltage during "on, stndby, sleep" mode. see table 5 and table 6 for all possible configurations. 0ch buck3_on[3:0] buck2 onstbymode[3:0] on mode standby mode 0000 off off 0001 pwm off 0010 reserved reserved 0011 pfm off 0100 pfm/pwm auto off 0101 pwm pwm 0110 pwm pfm/pwm auto 0111 reserved reserved 1000 pfm/pwm auto pfm/pwm auto 1001 reserved reserved 1010 reserved reserved 1011 reserved reserved 1100 pfm/pwm auto pfm 1101 pwm pfm 1110 reserved reserved 1111 reserved reserved 48 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 0fh: buck4_mode register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck4_mode r/w - - buck4_omode - initial value (master mode) 06h 0 0 0 0 0 1 1 0 initial value (slave mode) 06h 0 0 0 0 0 1 1 0 bit 5 : buck4_omode buck4 operational mode control when "pwron = h l"(slave mode only) 0 : off mode 1 : sleep mode bit 3-0 : buck4_onstbymode[3:0] buck4 operational mode control when in "on, standby" mode 0fh buck4_onstbymode[3:0] buck3 onstbymode[3:0] on mode standby mode 0000 off off 0001 pwm off 0010 reserved reserved 0011 pfm off 0100 pfm/pwm auto off 0101 pwm pwm 0110 pwm pfm/pwm auto 0111 reserved reserved 1000 pfm/pwm auto pfm/pwm auto 1001 reserved reserved 1010 reserved reserved 1011 reserved reserved 1100 pfm/pwm auto pfm 1101 pwm pfm 1110 reserved reserved 1111 reserved reserved address 0dh: buck3_mode register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck3_mode r/w - - buck3_omode - initial value (master mode) 06h 0 0 0 0 0 1 1 0 initial value (slave mode) 06h 0 0 0 0 0 1 1 0 bit 5 : buck3_omode buck3 operational mode control when "pwron = h l"(slave mode only) 0 : off mode 1 : sleep mode bit 3-0 : buck3_onstbymode[3:0] buck3 operational mode control when in "on, standby" mode 0dh buck3_onstbymode[3:0] address 0eh: buck4_volt register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck4_volt r/w - - - initial value (master mode) 10h 0 0 0 1 0 0 0 0 initial value (slave mode) 04h 0 0 0 0 0 1 0 0 bit 4-0 : buck4_on[4:0] sets the buck4 output voltage during "on, stndby, sleep" mode. see table 5 and table 6 for all possible configurations. 0eh buck4_on[4:0] buck4 onstbymode[3:0] on mode standby mode 0000 off off 0001 pwm off 0010 reserved reserved 0011 pfm off 0100 pfm/pwm auto off 0101 pwm pwm 0110 pwm pfm/pwm auto 0111 reserved reserved 1000 pfm/pwm auto pfm/pwm auto 1001 reserved reserved 1010 reserved reserved 1011 reserved reserved 1100 pfm/pwm auto pfm 1101 pwm pfm 1110 reserved reserved 1111 reserved reserved 49 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv ldo control ldox_en ldox_lpwr ldox_stby standby vox output 0 x x x off 1 0 0 x on 1 1 0 x low power 1 x 1 0 on 1 0 1 1 off 1 1 1 1 low power address 11h: ldo2_ctrl register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ldo2_ctrl r/w - - ldo3_lpwr ldo3_stby ldo2_lpwr ldo2_stby ldo1_lpwr ldo1_stby initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 5 : ldo3_lpwr enable low power mode for ldo3 see ldo control table. bit 4 : ldo3_stby set ldo3 output state when in standby. see ldo control table. bit 3 : ldo2_lpwr enable low power mode for ldo2 see ldo control table. bit 2 : ldo2_stby set ldo2 output state when in standby. see ldo control table. bit 1 : ldo1_lpwr enable low power mode for ldo1 see ldo control table. bit 0 : ldo1_stby set ldo1 output state when in standby. see ldo control table. 11h address 10h: ldo1_ctrl register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ldo1_ctrl r/w - - - vosnvs_sw_en dvref_en ldo3_en ldo2_en ldo1_en initial value (master mode) 11h 0 0 0 1 0 0 0 1 initial value (slave mode) 0fh 0 0 0 0 1 1 1 1 bit 4 : vosnvs_sw_en snvsen vosnvs power on/off control 0 : off / 1 : on bit 3 : dvref_en dvrefen ddrvref power on/off control 0 : off / 1 : on bit 2 : ldo3_en ldo3en ldo3 power on/off control 0 : off / 1 : on bit 1 : ldo2_en ldo2en ldo2 power on/off control 0 : off / 1 : on bit 0 : ldo1_en ldo1en ldo1 power on/off control 0 : off / 1 : on 10h address 13h: ldo2_volt register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ldo2_volt r/w - - initial value (master mode) 32h 0 0 1 1 0 0 1 0 initial value (slave mode) 14h 0 0 0 1 0 1 0 0 bit 5-0 : ldo2[5:0] sets the ldo2 output voltage. see table 5 and table 6 for all possible configurations. 13h ldo2[5:0] address 12h: ldo1_volt register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ldo1_volt r/w - - initial value (master mode) 08h 0 0 0 0 1 0 0 0 initial value (slave mode) 22h 0 0 1 0 0 0 1 0 bit 5-0 : ldo1[5:0] sets the ldo1 output voltage. see table 5 and table 6 for all possible configurations. 12h ldo1[5:0] 50 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 14h: ldo3_volt register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ldo3_volt r/w - - initial value (master mode) 32h 0 0 1 1 0 0 1 0 initial value (slave mode) 08h 0 0 0 0 1 0 0 0 bit 5-0 : ldo3[5:0] sets the ldo3 output voltage. see table 5 and table 6 for all possible configurations. 14h ldo3[5:0] address 16h: ldo_pden register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ldo_pden r/w - - - - dvref_pden ldo3_pden ldo2_pden ldo1_pden initial value (master mode) 0fh 0 0 0 0 1 1 1 1 initial value (slave mode) 0fh 0 0 0 0 1 1 1 1 bit 3 : dvref_pden dvref power-down discharge control 0 : power-down discharge disabled / 1 : power-down discharge enabled bit 2 : ldo3_pden ldo3 power-down discharge control 0 : power-down discharge disabled / 1 : power-down discharge enabled bit 1 : ldo2_pden ldo2 power-down discharge control 0 : power-down discharge disabled / 1 : power-down discharge enabled bit 0 : ldo1_pden ldo1 power-down discharge control 0 : power-down discharge disabled / 1 : power-down discharge enabled 16h address 17h: gpo register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 gpo r/w - gpo3_mode gpo2_mode gpo1_mode - gpo3_out gpo2_out gpo1_out initial value (master mode) 07h 0 0 0 0 0 1 1 1 initial value (slave mode) 07h 0 0 0 0 0 1 1 1 bit 6 : gpo3_mode gpo3 output mode setting 0 : open drain output mode 1 : cmos output mode bit 5 : gpo2_mode gpo2 output mode setting 0 : open drain output mode 1 : cmos output mode bit 4 : gpo1_mode gpo1 output mode setting 0 : open drain output mode 1 : cmos output mode bit 2 : gpo3_out gpo3 output setting at gpo3_mode=0 (open drain output mode) 0 : low 1 : hiz [open drain output mode] / high [cmos output mode] bit 1 : gpo2_out gpo2 output setting at gpo2_mode=0 (open drain output mode) 0 : low 1 : hiz [open drain output mode] / high [cmos output mode] bit 0 : gpo1_out gpo1 output setting at gpo1_mode=0 (open drain output mode) 0 : low 1 : hiz [open drain output mode] / high [cmos output mode] 17h address 15h: buck_pden register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 buck_pden r/w - - - - buck4_pden buck3_pden buck2_pden buck1_pden initial value (master mode) 0fh 0 0 0 0 1 1 1 1 initial value (slave mode) 0fh 0 0 0 0 1 1 1 1 bit 3 : buck4_pden buck4 power-down discharge control 0 : power-down discharge disabled / 1 : power-down discharge enabled bit 2 : buck3_pden buck3 power-down discharge control 0 : power-down discharge disabled / 1 : power-down discharge enabled bit 1 : buck2_pden buck2 power-down discharge control 0 : power-down discharge disabled / 1 : power-down discharge enabled bit 0 : buck1_pden buck1 power-down discharge control 0 : power-down discharge disabled / 1 : power-down discharge enabled 15h 51 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 19h: sec register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sec r/w - s40 s20 s10 s8 s4 s2 s1 initial value (master mode) xxh 0 x x x x x x x initial value (slave mode) xxh 0 x x x x x x x bit 6-0 : s1 to s40 second counter the second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00. (configured in bcd bianary-coded decimal)) any writing to the second counter resets divider units of less than 1 second. 19h address 18h: out32k register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 out32k r/w - - - - - - out32k_mode out32k_en initial value (master mode) 01h 0 0 0 0 0 0 0 1 initial value (slave mode) 01h 0 0 0 0 0 0 0 1 bit 1 : out32k_mode clk32kout output mode setting 0 : open drain output mode 1 : cmos output mode bit 0 : out32k_en clk32kout clock output enable 0 : disable [hiz] 1 : enable 18h 24 hour clock 12 hour clock 24 hour clock 12 hour clock 0 12(am0) 12 32(pm0) 1 01(am1) 13 21(pm1) 2 02(am2) 14 22(pm2) 3 03(am3) 15 23(pm3) 4 04(am4) 16 24(pm4) 5 05(am5) 17 25(pm5) 6 06(am6) 18 26(pm6) 7 07(am7) 19 27(pm7) 8 08(am8) 20 28(pm8) 9 09(am9) 21 29(pm9) 10 10(am10) 22 30(pm10) 11 11(am11) 23 31(pm11) address 1bh: hour register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hour r/w 12/24 - h20/pa h10 h8 h4 h2 h1 initial value (master mode) xxh 0 0 x x x x x x initial value (slave mode) xxh 0 0 x x x x x x bit 7 : 12/24 12hour clock or 24hour clock select bit. 0 : 12hour clock. 1 : 24hour clock. bit 5-0 : h20 to h1 hour counter the hour digits range as shown this table and are carried to the day-of-month and day-of-week digits in transition from pm11 to am12 or from 23 to 00.(configured in bcd bianary-coded decimal)) 1bh address 1ah: min register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 min r/w - m40 m20 m10 m8 m4 m2 m1 initial value (master mode) xxh 0 x x x x x x x initial value (slave mode) xxh 0 x x x x x x x bit 6-0 : m1 to m40 minute counter the minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00. (configured in bcd bianary-coded decimal)) 1ah 52 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 1fh: year register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 year r/w y80 y40 y20 y10 y8 y4 y2 y1 initial value (master mode) xxh x x x x x x x x initial value (slave mode) xxh x x x x x x x x bit 7-0 : y80 to y1 year counter the year digits (y80 to y1) range from 00 to 99 and are carried to the 19/20 digits in reversion from 99 to 00. 00, 04, 08, ..., 92 and 96 in leap years.(configured in bcd bianary-coded decimal)) 1fh address 1eh: month register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 month r/w - - - mo10 mo8 mo4 mo2 mo1 initial value (master mode) xxh 0 0 0 x x x x x initial value (slave mode) xxh 0 0 0 x x x x x bit 4-0 : mo10 to mo1 month counter the month digits (mo10 to mo1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1. (configured in bcd bianary-coded decimal)) 1eh address 21h: alm0_min register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm0_min r/w - a0m40 a0m20 a0m10 a0m8 a0m4 a0m2 a0m1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 6-0 : a0m40 to a0m1 alarm0 minute threshold value.(configured in bcd bianary-coded decimal)) 21h address 20h: alm0_sec register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm0_sec r/w - a0s40 a0s20 a0s10 a0s8 a0s4 a0s2 a0s1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 6-0 : a0s40 to a0s1 alarm0 second threshold value.(configured in bcd bianary-coded decimal)) 20h address 1ch: week register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 week r/w - - - - - w4 w2 w1 initial value (master mode) 0xh 0 0 0 0 0 x x x initial value (slave mode) 0xh 0 0 0 0 0 x x x bit 2-0 : w4 to w1 day-of-week counter the day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits. (configured in bcd bianary-coded decimal)) correspondences between days of the week and the day-of-week digit are user-definable. (ex. sunday = 0, 0, 0) the writing of (1, 1, 1) to (w4, w2, w1) is prohibited except when days of the week are unused. 1ch address 1dh: day register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 day r/w - - d20 d10 d8 d4 d2 d1 initial value (master mode) xxh 0 0 x x x x x x initial value (slave mode) xxh 0 0 x x x x x x bit 5-0 : d20 to d1 day-of-month counter the day-of-month digits (d20 to d1) range from 1 to 31 for january, march, may, july, august, october, and december, from 1 to 30 for april, june, september, and november, from 1 to 29 for february in leap years, from 1 to 28 for february in ordinary years. the day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. (configured in bcd bianary-coded decimal)) 1dh 53 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 22h: alm0_hour register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm0_hour r/w a0_12/24 - a0h20/pa a0h10 a0h8 a0h4 a0h2 a0h1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : a0_1224 12hour clock / 24hour clock select bit. bit 5-0 : a0h20/pa, a0h40 to a0h1 alarm0 hour threshold value.(configured in bcd bianary-coded decimal)) 22h address 23h: alm0_week register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm0_week r/w - - - - - a0w4 a0w2 a0w1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 2-0 : a0w4 to a0w1 alarm0 day of the week threshold value.(configured in bcd bianary-coded decimal)) 23h address 24h: alm0_day register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm0_day r/w - - a0d20 a0d10 a0d8 a0d4 a0d2 a0d1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 5-0 : a0d20 to a0d1 alarm0 day threshold value.(configured in bcd bianary-coded decimal)) 24h address 27h: alm1_sec register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm1_sec r/w - a1s40 a1s20 a1s10 a1s8 a1s4 a1s2 a1s1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 6-0 : a1s40 to a1s1 alarm1 second threshold value.(configured in bcd bianary-coded decimal)) 27h address 25h: alm0_month register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm0_month r/w - - - a0mo10 a0mo8 a0mo4 a0mo2 a0mo1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 4-0 : a0mo10 to a0mo1 alarm0 month threshold value.(configured in bcd bianary-coded decimal)) 25h address 26h: alm0_year register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm0_year r/w a0y80 a0y40 a0y20 a0y10 a0y8 a0y4 a0y2 a0y1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7-0 : a0y80 to a0y1 alarm0 year threshold value 26h 54 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 2dh: alm1_year register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm1_year r/w a1y80 a1y40 a1y20 a1y10 a1y8 a1y4 a1y2 a1y1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7-0 : a1y80 to a1y1 alarm1 year threshold value.(configured in bcd bianary-coded decimal)) 2dh address 2ch: alm1_month register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm1_month r/w - - - a1mo10 a1mo8 a1mo4 a1mo2 a1mo1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 4-0 : a1mo10 to a1mo1 alarm1 month threshold value.(configured in bcd bianary-coded decimal)) 2ch address 2bh: alm1_day register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm1_day r/w - - a1d20 a1d10 a1d8 a1d4 a1d2 a1d1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 5-0 : a1d20 to a1d1 alarm1 day threshold value.(configured in bcd bianary-coded decimal)) 2bh address 29h: alm1_hour register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm1_hour r/w a1_12/24 - a1h20/pa a1h10 a1h8 a1h4 a1h2 a1h1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : a1_12/24 12hour clock / 24hour clock select bit. bit 5-0 : a1h20/pa, a1h10 to a1h1 alarm1 hour threshold value.(configured in bcd bianary-coded decimal)) 29h address 2ah: alm1_week register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm1_week r/w - - - - - a1w4 a1w2 a1w1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 2-0 : a1w4 to a1w1 alarm1 day of the week threshold value.(configured in bcd bianary-coded decimal)) 2ah address 28h: alm1_min register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm1_min r/w - a1m40 a1m20 a1m10 a1m8 a1m4 a1m2 a1m1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 6-0 : a1m80 to a1m1 alarm1 minute threshold value.(configured in bcd bianary-coded decimal)) 28h 55 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 2eh: alm0_mask register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm0_mask r/w a0_onesec a0_year a0_mon a0_day a0_week a0_hour a0_min a0_sec initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : a0_onesec alarm0 interrupt occur once every second. (synchronized with second counter increment) 0 : disable 1 : enable regardless of any other setting in the alm0_mask register and the contents of the respective alm0_sec to alm0_year registers. bit 6-0 : a0_year to a0_sec alarm0 interrupt threshold mask bit. 0 : mask 1 : non-mask 2eh address 2fh: alm1_mask register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm1_mask r/w a1_onesec a1_year a1_mon a1_day a1_week a1_hour a1_min a1_sec initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : a1_onesec alarm1 interrupt occur once every second. (synchronized with second counter increment) 0 : disable 1 : enable regardless of any other setting in the alm1_mask register and the contents of the respective alm1_sec to alm1_year registers. bit 6-0 : a1_year to a1_sec alarm1 interrupt threshold mask bit. 0 : mask 1 : non-mask 2fh address 30h: alm2 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm2 r/w - - - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 1-0 : alm2[1:0] invalidate alarm2 when change the value of clock and calendar. 00 : off (initial state) 01 : once per 1 second (synchronized with second counter increment) 10 : once per minute (at 00 seconds of every minute) 11 : once per hour (at 00 minutes, and 00 seconds of every hour) 30h alm2[1:0] address 31h: trim register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 trim r/w dev initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : dev 0 : the oscillation adjustment circuit operates 00, 30 seconds. 1 : the oscillation adjustment circuit operates 00 seconds. bit 6-0 : trim[6:0] the oscillation adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register at the timing set by dev. the oscillation adjustment circuit will not operate with the same timing (00, or 30 seconds ) as the timing of writing to the oscillation adjustment register. trim[6] : bit setting of '0' causes an increment (trim[5:0]-1) x 2 of time counts by. trim[6] : bit setting of '1' causes a decrement (trim[5:0]+1) x 2 of time counts by. trim[6:0] : bit setting of "x00000x" causes neither an increment nor decrement of time counts. 31h trim[6:0] 56 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 34h: chg_state register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_state r - initial value (master mode) xxh 0 x x x x x x x initial value (slave mode) xxh 0 x x x x x x x bit 6-0 : chg_state[6:0] the current state of the battery charger. table shows the details of the register values. 34h chg_state[6:0] address 33h: sys_init register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sys_init r/w - - - - - - chgrst - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 1(w) : chgrst 0 : releases reset operation 1 : resets battery charger block the related control registers are not initialized. 33h chg_state state description 00h suspend suspend charging 01h trickle charge trickle charging (pre-conditioning) 02h pre charge pre-charging 03h fast charge fast charging 0dh batdet battery detection 0eh top off reached to termination current 0fh done charging finished 10h temp err 1 out of standard temperature while pre charge state 11h temp err 2 out of standard temperature while fast charge or topoff state 12h temp err 3 out of standard temperature while done state 13h temp err 4 out of standard temperature while suspend state 14h temp err 5 out of standard temperature while pre charge state 20h tsd 1 thermal shut down while pre charge state ( > tjmax) 21h tsd 2 thermal shut down while fast charge state ( > tjmax) 22h tsd 3 thermal shut down while top off state ( > tjmax) 23h tsd 4 thermal shut down while done state ( > tjmax) 24h tsd 5 thermal shut down while trickle charge state ( > tjmax) 30h batt assist 1 vsys < vbat while fast charge state 31h batt assist 2 vsys < vbat while top off state 32h batt assist 3 vsys < vbat after top off state (done) 7fh batt error battery error others (reserved) - address 35h: chg_last_state register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_last_state r - initial value (master mode) xxh 0 x x x x x x x initial value (slave mode) xxh 0 x x x x x x x bit 6-0 : chg_last_state[6:0] the previous state of the battery charger. table shows the details of the register values. 35h chg_last_state[6:0] address 32h: conf register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 conf r/w - - - - - - xstb pon initial value (master mode) 01h 0 0 0 0 0 0 0 1 initial value (slave mode) 01h 0 0 0 0 0 0 0 1 bit 1 : xstb oscillation halt sensing monitor bit. 0 : sensing a halt of oscillation 1 : sensing a normal condition of oscillation. the xstb accepts the reading and writing of "0" and "1". the xstb bit will be set to "0" when the oscillation halt sensing. the xstb bit will hold "0" even after the restart of oscillation. bit 0 : pon power-on-reset flag. 0 : normal condition 1 : detecting power-on-reset the pon bit will be set to "1" when supply voltage above the snvs uvlo setting. the pon bit will hold the setting of "1" even after power-on. the pon bit accepts only the writing of "0". when pon bit set to "0", snvs uvlo behave intermittent monitoring mode. 32h 57 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 38h: vsys_stat register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vsys_stat r - - - - - - vsys_lo vsys_uvn initial value (master mode) 0xh 0 0 0 0 0 0 x x initial value (slave mode) 0xh 0 0 0 0 0 0 x x bit 1 : vsys_lo vsys low voltage detection status 0 : vsys < vsys_min 1 : vsys > vsys_max bit 0 : vsys_uvn vsys uvlo detection status 0 : low voltage 1 : normal voltage 38h address 37h: dcin_stat register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dcin_stat r - - - - dcin_ov inhibit (note1) dcin_clps dcin_det initial value (master mode) 0xh 0 0 0 0 x x x x initial value (slave mode) 0xh 0 0 0 0 x x x x bit 3 : dcin_ov dcin over-voltage status 0 : normal voltage 1 : dcin > 6.5v bit 2 : inhibit (note1) for rohm factory only bit 1 : dcin_clps dcin anti-collapse status 0 : normal operation 1 : anti-collapse bit 0 : dcin_det dcin detection status 0 : not detected or low level 1 : dcin detected (over uvlo level) 37h address 36h: bat_stat register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bat_stat r - - bat_det bat_det_done vbat_ov low_bat vbat_short dbat_det initial value (master mode) xxh 0 0 x x x x x x initial value (slave mode) xxh 0 0 x x x x x x bit 5 : bat_det battery detection result 0 : battery removed or no battery detected 1 : battery presence bit 4 : bat_det_done battery detection status 0 : detection running 1 : detection finished bit 3 : vbat_ov vbat over-voltage status 0 : vbat < vbat_ovp - 150mv (hysteresis) 1 : vbat > vbat_ovp for example, vbat_ov might be detected when the battery is removed while fast charging. bit 2 : low_bat battery low-voltage status 0 : vbat > vbat_lo 1 : vbat < vbat_lo while dcinok bit 1 : vbat_short battery short-circuits detection status 0 : vbat > 1.6v (hysteresis) 1 : vbat < 1.5v bit 0 : dbat_det dead battery detection status 0 : not detected 1 : detected vbat keeps under vbat_lo until the timer is expired, the battery is assumed as a weak battery or a dead battery. the timer expiration time is set by tim_dbp register. 36h 58 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 3bh: bat_temp register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bat_temp r - - - - - initial value (master mode) 0xh 0 0 0 0 0 x x x initial value (slave mode) 0xh 0 0 0 0 0 x x x bit 2-0 : bat_temp[2:0] the temperature thresholds have hysteresis. table lists the temperature threshold values. 3bh bat_temp[2:0] address 3ah: chg_wdt_stat register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_wdt_stat r initial value (master mode) xxh x x x x x x x x initial value (slave mode) xxh x x x x x x x x bit 7-0 : chgwdts[7:0] actual watch-dog timer counter value for pre-charging & tricle-charging or fast charging & top off. pchg(or tchg) : (chgwdts -1) x (64/60) min. fchg(or toff) : (chgwdts * 8 -240) * (64/60/2) min. fchg(or toff) cold1 condition : (chgwdts * 8 -3) * (64/60) min. 3ah chgwdts[7:0] address 39h: chg_stat register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_stat r - - - - - - - vrechg_det initial value (master mode) 0xh 0 0 0 0 0 0 0 x initial value (slave mode) 0xh 0 0 0 0 0 0 0 x bit 0 : vrechg_det re-charge voltage detection status voltage. 0 : vbat > vbat_mnt 1 : vbat < vbat_mnt 39h bat_temp temperature range description 0h room temp t2 < tbat < t3 1h hot1 t3 < tbat < t5 2h hot2 t5 < tbat < t4 3h hot3 t4 < tbat 4h cold1 t1 < tbat < t2 5h cold2 tbat < t1 6h temp. disable disable thermal control (no thermistor) 7h battery open ts port is open no. description default value note 1 lower threshold of t1 2 deg. t1 in jeita profile 2 upper threshold of t1 5 deg. t1 in jeita profile 3 lower threshold of t2 10 deg. t2 in jeita profile 4 upper threshold of t2 13 deg. t2 in jeita profile 5 lower threshold of t3 42 deg. t3 in jeita profile 6 upper threshold of t3 45 deg. t3 in jeita profile 7 lower threshold of t4 55 deg. t4 in jeita profile 8 upper threshold of t4 58 deg. t4 in jeita profile 9 lower threshold of t5 47 deg. between t3 and t4 10 upper threshold of t5 50 deg. between t3 and t4 59 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 3eh: dcin_clps register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dcin_clps r/w initial value (master mode) 36h 0 0 1 1 0 1 1 0 initial value (slave mode) 36h 0 0 1 1 0 1 1 0 bit 7-0 : dcin_clps[7:0] dcin anti-collapse entry voltage threshold 0 v to 20.4 v range, 80 mv steps. when dcin < dcin_clps is detected, the charger decrease the charging current. dcin_clps voltage must set to be higher than vbat_chg. 3eh dcin_clps[7:0] address 40h: vsys_max register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vsys_max r/w - initial value (master mode) 23h 0 0 1 0 0 0 1 1 initial value (slave mode) 21h 0 0 1 0 0 0 0 1 bit 6-0 : vsys_max[6:0] vsys voltage rising detection threshold 0.5v to 7.0v range, 0.1v steps 40h vsys_max[6:0] address 3fh: vsys_reg register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vsys_reg r/w - - - inhibit (note1) initial value (master mode) 09h 0 0 0 0 1 0 0 1 initial value (slave mode) 09h 0 0 0 0 1 0 0 1 bit 4 : inhibit (note1) for rohm factory only bit 3-0 : vsys_reg[3:0] vsys regulation voltage setting 4.2v to 5.25v range 3fh vsys_reg[3:0] dcin_clps threshold voltage 00h 0.0v ~ ~ 33h 3.08v 34h 3.16v 35h 3.24v 36h 3.32v 37h 3.40v 38h 3.48v 39h 3.56v 3ah 3.64v 3bh 3.72v 3ch 3.80v 3dh 3.88v 3eh 3.96v ~ ~ ffh 20.4v vsys_reg vsys voltage 00h 4.20 v 01h 4.30 v 02h 4.40 v 03h 4.45 v 04h 4.50 v 05h 4.55 v 06h 4.60 v 07h 4.65 v 08h 4.70 v 09h 4.75 v 0ah 4.80 v 0bh 4.85 v 0ch 4.90 v 0dh 4.95 v 0eh 5.00 v 0fh 5.25 v 60 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv vsys_max vsys_min vsys voltage 05h-15h 0.5v - 2.1 v 16h 2.2 v 17h 2.3 v 18h 2.4 v 19h 2.5 v 1ah 2.6 v 1bh 2.7 v 1ch 2.8 v 1dh 2.9 v 1eh 3.0 v 1fh 3.1 v 20h 3.2 v 21h 3.3 v 22h 3.4 v 23h 3.5 v 24h 3.6 v 25h-41h 3.7v - 7.0v address 42h: chg_set1 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_set1 r/w wdt_dis wdt_auto auto_fst fst_trg auto_rechg btmp_en cold_err_en chg_en initial value (master mode) 6fh 0 1 1 0 1 1 1 1 initial value (slave mode) 6fh 0 1 1 0 1 1 1 1 bit 7 : wdt_dis disable charger wdt 0 : normal operation 1 : disable when wdt_dis = "0", the charger will stop charging when the wdt expired. it means something error has been occurred. setting wdt_dis = "1", the host should handle any error by its software. bit 6 : wdt_auto wdt setting mode 0 : manual setting 1 : auto setting at the auto setting mode, the wdt expiration time is set to 128 minutes for pre-charging and 640 minites for fast-charging. in the manual setting mode, the wdt expiration time is set by the register wdt_pre for pre-charging and the register wdt_fst for fast-charging. bit 5 auto_fst fast charging transition mode 0 : manual control 1 : auto control when vbat > vpre_hi is detected at pre-charging, the charger goes to fast charging. in the manual control mode, the host should write fst_trg = "1" to move the charger to fast charging. bit 4 fst_trg trigger to move to fast charging 0 : no action 1 : generate the trigger see auto_fst. in using this register, please set auto_fst as '0'. bit 3 auto_rechg automatic re-charging mode 0 : manual control 1 : auto control in the auto control mode, the charger will re-start charging when the maintenance voltage detected (vbat < vbat_mnt). while the manual control mode, vbat_mnt can be detected but re-charging should be entered by the software. bit 2 btmp_en charging voltage is reduced by battery temperature. 0 : disable 1 : enable bit 1 cold_err_en slow down the watch-dog timer counter in cold1 condition 0 : disable count down per 4.27min 1 : enable count down per 8.53min bit 0 chg_en enabling charger operation 0 : disable 1 : enable 42h address 41h: vsys_min register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vsys_min r/w - initial value (master mode) 21h 0 0 1 0 0 0 0 1 initial value (slave mode) 1fh 0 0 0 1 1 1 1 1 bit 6-0 : vsys_min[6:0] vsys voltage rising detection threshold 0.5v to 7.0v range, 0.1v steps 41h vsys_min[6:0] 61 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv ipre pre-charging current 0h 0 ma 1h 50 ma 2h 100 ma 3h 150 ma 4h 200 ma 5h 250 ma 6h 300 ma 7h 350 ma 8h 400 ma 9h 450 ma ah 500 ma bh-fh (reserved) address 45h: chg_wdt_fst register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 45h chg_wdt_fst r/w initial value (master mode) 26h 0 0 1 0 0 1 1 0 initial value (slave mode) 26h 0 0 1 0 0 1 1 0 bit 7-0 : wdt_fst[7:0] watch dog timer setting for fast charging 8.5 to 2176 minutes range, 512-sec steps this register is effective only when '0' is written to wdt_auto(address 42h bit6). fchg(or toff) : (chgwdts * 8 -240) * (64/60/2) min. fchg(or toff) cold1 condition : (chgwdts * 8 -3) x (64/60) min. wdt_fst[7:0] address 46h: chg_ipre register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_ipre r/w initial value (master mode) 52h 0 1 0 1 0 0 1 0 initial value (slave mode) 52h 0 1 0 1 0 0 1 0 bit 7-4 : itri[3:0] trickle charge current setting 10 ma to 100 ma range, 10 ma steps bit 3-0 : ipre[3:0] pre-charging current setting 50 ma to 500 ma range, 50 ma steps. 46h itri[3:0] ipre[3:0] tim_cnt_sel[2:0] timer setting (clk32k cycle) 0h 1600 (48.8ms) 1h 3200 (97.7ms) 2h 4800 (146.5ms) 3h 6400 (195.3ms) itri trickle charging current 0h 0 ma 1h 10 ma 2h 20 ma 3h 30 ma 4h 40 ma 5h 50 ma 6h 60 ma 7h 70 ma 8h 80 ma 9h 90 ma ah 100 ma bh-fh (reserved) address 43h: chg_set2 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_set2 r/w vf_treg_en - rebatdet batdet_en - - initial value (master mode) 90h 1 0 0 1 0 0 0 0 initial value (slave mode) 90h 1 0 0 1 0 0 0 0 bit 7 : vf_treg_en thermal shutdown for charger 0 : disable / 1 : enable bit 5 : rebatdet trigger for re-trial of the battery detection 0 : release the operation / 1 : start detection bit 4 : batdet_en enabling battery detection 0 : disable / 1 : enable bit 1-0 : tim_cnt_sel[1:0] transition timer setting from the suspend state to the trickle state 43h tim_cnt_sel[1:0] address 44h: chg_wdt_pre register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_wdt_pre r/w initial value (master mode) 1eh 0 0 0 1 1 1 1 0 initial value (slave mode) 1eh 0 0 0 1 1 1 1 0 bit 7-0 : wdt_pre[7:0] watch dog timer setting for pre-charging 1 to 272 minutes range, 64-sec steps this register is effective only when '0' is written to wdt_auto(address 42h bit6). pchg(or tchg) : (chgwdts -1) * (64/60) min. 44h wdt_pre[7:0] 62 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv ifst fast charging current 00h 0 ma 01h 100 ma 02h 200 ma 03h 300 ma 04h 400 ma 05h 500 ma 06h 600 ma 07h 700 ma 08h 800 ma 09h 900 ma 0ah 1000 ma 0bh 1100 ma 0ch 1200 ma 0dh 1300 ma 0eh 1400 ma 0fh 1500 ma 10h 1600 ma 11h 1700 ma 12h 1800 ma 13h 1900 ma 14h 2000 ma 15h-1f (reserved) ichg_term termination current 0h 0 ma 1h 10 ma 2h 20 ma 3h 30 ma 4h 40 ma 5h 50 ma 6h 100 ma 7h 150 ma 8h 200 ma 9h-f (reserved) address 47h: chg_ifst register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_ifst r/w - - - initial value (master mode) 04h 0 0 0 0 0 1 0 0 initial value (slave mode) 04h 0 0 0 0 0 1 0 0 bit 4-0 ifst[4:0] battery charging current for fast charge 100 ma to 2000 ma range, 100 ma steps 47h ifst[4:0] address 48h: chg_ifst_term register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_ifst_term r/w - - - - initial value (master mode) 05h 0 0 0 0 0 1 0 1 initial value (slave mode) 05h 0 0 0 0 0 1 0 1 bit 3-0 : ifst_term[3:0] charging termination current for fast charge 10 ma to 200 ma range 48h ifst_term[3:0] 63 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv vpre_hi vpre_lo setting voltage 0h 2.1 v 1h 2.2 v 2h 2.3 v 3h 2.4 v 4h 2.5 v 5h 2.6 v 6h 2.7 v 7h 2.8 v 8h 2.9 v 9h 3.0 v ah 3.1 v bh 3.2 v ch 3.3 v dh 3.4 v eh 3.5 v fh 3.6 v vbat_chgx setting voltage 00h 3.72 v 01h 3.74 v 02h 3.76 v 03h 3.78 v 04h 3.80 v ~ ~ 1dh 4.30 v 1eh 4.32 v 1fh 4.34 v address 4bh: chg_vbat_2 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_vbat_2 r/w - - - initial value (master mode) 13h 0 0 0 1 0 0 1 1 initial value (slave mode) 13h 0 0 0 1 0 0 1 1 bit 4-0 : vbat_chg2[4:0] fast charging voltage for the temperature range t3-t5 4bh vbat_chg2[4:0] address 4ch: chg_vbat_3 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_vbat_3 r/w - - - initial value (master mode) 10h 0 0 0 1 0 0 0 0 initial value (slave mode) 10h 0 0 0 1 0 0 0 0 bit 4-0 : vbat_chg3[4:0] fast charging voltage for the temperature range t5-t4 and t2-t1 4ch vbat_chg3[4:0] address 49h: chg_vpre register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_vpre r/w initial value (master mode) c9h 1 1 0 0 1 0 0 1 initial value (slave mode) c9h 1 1 0 0 1 0 0 1 bit 7-4 : vpre_hi[3:0] upper threshold of pre-charging voltage 2.1v to 3.6v range, 0.1v steps. bit 3-0 : vpre_lo[3:0] lower threshold of pre-charging voltage 2.1v to 3.6v range, 0.1v steps. vpre_lo is also the upper threshold of trickle charging voltage. 49h vpre_hi[3:0] vpre_lo[3:0] address 4ah: chg_vbat_1 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_vbat_1 r/w - - - initial value (master mode) 18h 0 0 0 1 1 0 0 0 initial value (slave mode) 18h 0 0 0 1 1 0 0 0 bit 4-0 : vbat_chg1[4:0] fast charging voltage for the temperature range t2-t3 (room) 4ah vbat_chg1[4:0] 64 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 4dh: chg_led_1 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chg_led_1 r/w - - - - - initial value (master mode) 03h 0 0 0 0 0 0 1 1 initial value (slave mode) 03h 0 0 0 0 0 0 1 1 bit 2-0 : terr[2:0] chgled lighting setting for the battery charging temperature error indication. 4dh terr[2:0] address 4eh: vf_th register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vf_th r/w initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7-0 : vf_th[7:0] vf voltage threshold for monitor 0.100v to 1.395v range, 1.3v/256 steps 4eh vf_th[7:0] terr_tout led lighting for error indication 0h always lighting on 1h blinking in 0.128 hz 2h blinking in 0.256 hz 3h blinking in 0.512 hz 4h blinking in 1 hz 5h blinking in 4 hz 6h blinking in 8 hz 7h light off c h a r g i n g v o l t a g e t e m p e r r a t u r e o f b a t t e r y p a c k v b a t _ c h g 1 v b a t _ c h g 2 v b a t _ c h g 3 t 1 t 2 t 3 t 5 t 4 c h a r g i n g v o l t a g e t e m p e r r a t u r e o f b a t t e r y p a c k v b a t _ c h g 1 v b a t _ c h g 2 v b a t _ c h g 3 t 1 t 2 t 3 t 5 t 4 b t m p _ e n = 0 ( a d d r e s s 4 2 h b i t 2 ) b t m p _ e n = 1 ( a d d r e s s 4 2 h b i t 2 ) address 4fh: bat_set_1 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bat_set_1 r/w initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7-4 : vbat_hi[3:0] battery voltage threshold for vbat rising 3.00v to 3.60v range, 50 mv steps. bit 3-0 : vbat_lo[3:0] battery voltage threshold for vbat falling 2.50v to 3.10v range, 50 mv steps. vbat_lo is also the lower threshold of dead battery detection. 4fh vbat_hi[3:0] vbat_lo[3:0] vbat_hi setting voltage vbat_lo setting voltage 0h 3.00 v 0h 2.50 v 1h 3.05 v 1h 2.55 v 2h 3.10 v 2h 2.60 v 3h 3.15 v 3h 2.65 v 4h 3.20 v 4h 2.70 v 5h 3.25 v 5h 2.75 v 6h 3.30 v 6h 2.80 v 7h 3.35 v 7h 2.85 v 8h 3.40 v 8h 2.90 v 9h 3.45 v 9h 2.95 v ah 3.50 v ah 3.00 v bh 3.55 v bh 3.05 v ch 3.60 v ch 3.10 v dh 3.65 v dh 3.15 v eh 3.70 v eh 3.20 v fh 3.75 v fh 3.25 v 65 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv tim_dbp dbp timer setting 0h 12 min 1h 32 min 2h 45 min 3h 64 min 4h 128 min 5h 5 min 6h 1 min 7h 0 min vbat_mnt setting voltage 0h vbat_chg1/2/3 - 0.35v 1h vbat_chg1/2/3 - 0.30v 2h vbat_chg1/2/3 - 0.25v 3h vbat_chg1/2/3 - 0.20v 4h vbat_chg1/2/3 - 0.15v 5h vbat_chg1/2/3 - 0.10v 6h vbat_chg1/2/3 - 0.05v 7h vbat_chg1/2/3 - 0.00v vbat_ovp setting voltage 0h 4.40 v 1h 4.45 v 2h 4.50 v 3h 4.55 v 4h 4.60 v 5h 4.65 v 6h 4.70 v 7h 4.75 v 8h 4.80 v 9h - fh (reserved) address 53h: alm_vbat_th_l register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm_vbat_th_l r/w initial value (master mode) ffh 1 1 1 1 1 1 1 1 initial value (slave mode) ffh 1 1 1 1 1 1 1 1 vbat_th[8:0] battery voltage alarm threshold setting range is from 0.00v to 8.176v, 16mv steps. see also vbat_mon_det/res alarm. 53h vbat_th[7:0] address 52h: alm_vbat_th_u register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm_vbat_th_u r/w - - - - - - - vbat_th[8] initial value (master mode) 01h 0 0 0 0 0 0 0 1 initial value (slave mode) 01h 0 0 0 0 0 0 0 1 52h address 51h: bat_set_3 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bat_set_3 r/w - - - - - initial value (master mode) 02h 0 0 0 0 0 0 1 0 initial value (slave mode) 02h 0 0 0 0 0 0 1 0 bit 2-0 : tim_dbp[2:0] dead battery provisioning timer setting refer to the description for dbat_det. 51h tim_dbp[2:0] address 50h: bat_set_2 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bat_set_2 r/w - initial value (master mode) 30h 0 0 1 1 0 0 0 0 initial value (slave mode) 30h 0 0 1 1 0 0 0 0 bit 7-4 : vbat_ovp[3:0] battery over-voltage detection threshold. 4.40v to 4.80v range, 50 mv steps bit 2-0 : vbat_mnt[2:0] battery voltage maintenance threshold. the charger starts re-charging when vbat < vbat_mnt. 50h vbat_ovp[3:0] vbat_mnt[2:0] 66 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 59h: vm_vbat_l register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_vbat_l r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 vbat[12:0] measured battery voltage 0 v to 8.191 v range, 1mv steps. this register value is also used for over-voltage detection and some charger functions. 59h vbat[7:0] address 58h: vm_vbat_u register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_vbat_u r - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 58h vbat[12:8] address 55h: alm_vsys_th register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm_vsys_th r/w initial value (master mode) ffh 1 1 1 1 1 1 1 1 initial value (slave mode) ffh 1 1 1 1 1 1 1 1 vsys_th[7:0] vsys voltage alarm threshold setting range is from 0v to 12.75v, 50mv steps. 55h vsys_th[7:0] address 54h: alm_dcin_th register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 alm_dcin_th r/w initial value (master mode) 0fh 0 0 0 0 1 1 1 1 initial value (slave mode) 0fh 0 0 0 0 1 1 1 1 dcin_th[7:0] dcin voltage alarm threshold setting range is from 0v to 20.4v, 80mv steps. 54h dcin_th[7:0] address 57h: vm_ibat_l register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ibat_l r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 ibat[11:0] measured battery current 0 a to 4.095 a range, 1ma steps. 57h ibat[7:0] address 56h: vm_ibat_u register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ibat_u r - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 56h ibat[11:8] 67 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 5ah: vm_btmp register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_btmp r/w initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7-0 : btmp[7:0] measured / preset battery temperature -55 to 200 deg. celsius, 1-degree steps. (r) btmp is measured at the same time of measuring vth. (w) btmp is effective when a thermistor does not exist. 5ah btmp[7:0] address 5bh: vm_vth register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_vth r/w initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7-0 : vth[7:0] thermistor terminal (ts) voltage 0.1 v to 1.395 v range, 1.3/256 v steps. 5bh vth[7:0] address 5ch: vm_dcin_u register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_dcin_u r - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 5ch dcin[11:8] address 5fh: vm_vf register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_vf r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7-0 : vf[7:0] vf voltage threshold for monitor 0.1 v to 1.395 v range, 1.3/256 v steps. 5fh vf[7:0] address 5eh: vm_vsys register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_vsys r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7-0 : vsys[7:0] measured vsys voltage 0 v to 12.75 v range, 50 mv steps. 5eh vsys[7:0] address 5dh: vm_dcin_l register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_dcin_l r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 dcin[11:0] measured dcin voltage 0 v to 20.475 v range, 5mv steps. 5dh dcin[7:0] 68 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 64h: vm_ibatload_pst_u register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ibatload_pst_u r - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 64h ibat_batload_pst[11:8] address 65h: vm_ibatload_pst_l register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ibatload_pst_l r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 ibat_batload_pst[11:0] measured battery current while in load when battery detection 0 a to 4.095 a range, 1 ma steps. 65h ibat_batload_pst[7:0] address 62h: vm_vbatload_pre_u register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_vbatload_pre_u r - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 62h vbat_batload_pre[12:8] address 63h: vm_vbatload_pre_l register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_vbatload_pre_l r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 vbat_batload_pre[12:0] measured battery voltage previous to load when battery detection 0 v to 8.191 v range, 1 mv steps. 63h vbat_batload_pre[7:0] address 66h: vm_vbatload_pst_u register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_vbatload_pst_u r - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 66h vbat_batload_pst[12:8] address 61h: vm_ibatload_pre_l register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ibatload_pre_l r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 vbat_batload_pre[11:0] measured battery current previous to load when battery detection 0 a to 4.095 a range, 1 ma steps. 61h ibat_batload_pre[7:0] address 60h: vm_ibatload_pre_u register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ibatload_pre_u r - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 60h ibat_batload_pre[11:8] 69 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 6ah: vm_sma_ibat_u register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_sma_ibat_u r - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 6ah ibat_sma[11:8] address 6bh: vm_sma_ibat_l register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_sma_ibat_l r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 ibat_sma[11:0] measured battery current caluculated simple moving average 0 a to 4.095 a range, 1ma steps. 6bh ibat_sma[7:0] address 6dh: cc_ctrl register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_ctrl r/w ccntrst ccntenb cc_calib - - - - - initial value (master mode) 40h 0 1 0 0 0 0 0 0 initial value (slave mode) 40h 0 1 0 0 0 0 0 0 bit7 : ccntrst reset the coulomb counter 0 : release resetting 1 : reset cc_ccntd_3-0 this reset is "pulse reset type", is not always reset. bit6 : ccntenb enabling the coulomb counter 0 : disable (stop counting) 1 : enable (counting) bit5 : cc_calib calibration mode selection for the coulomb counter 0 : a calibration is carried out automatically. 1 : a calibration is carried out compulsorily. 6dh address 67h: vm_vbatload_pst_l register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_vbatload_pst_l r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 ibat_batload_pst[12:0] measured battery current while in load when battery detection 0 a to 8.191 a range, 1ma steps. 67h vbat_batload_pst[7:0] address 69h: vm_sma_vbat_l register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_sma_vbat_l r initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 vbat_sma[12:0] measured battery voltage calucurated simple moving average 0 v to 8.191 v range, 1 mv steps. 69h vbat_sma[7:0] address 68h: vm_sma_vbat_u register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_sma_vbat_u r - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 68h vbat_sma[12:8] 70 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 72h: cc_batcap3_th_u register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_batcap3_th_u r/w - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 72h cc_batcap3_th[11:8] address 70h: cc_batcap2_th_u register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_batcap2_th_u r/w - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 70h cc_batcap2_th[11:8] address 71h: cc_batcap2_th_l register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_batcap2_th_l r/w initial value (master mode) 3fh 0 0 1 1 1 1 1 1 initial value (slave mode) 3fh 0 0 1 1 1 1 1 1 cc_batcap2_th[11:0] battery capacity monitor threshold2 71h cc_batcap2_th[7:0] address 6eh: cc_batcap1_th_u register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_batcap1_th_u r/w - - - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 6eh cc_batcap1_th[11:8] address 6fh: cc_batcap1_th_l register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_batcap1_th_l r/w initial value (master mode) 7eh 0 1 1 1 1 1 1 0 initial value (slave mode) 7eh 0 1 1 1 1 1 1 0 cc_batcap1_th[11:0] battery capacity monitor threshold1 6fh cc_batcap1_th[7:0] address 74h: cc_stat register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_stat r - - - - - cc_mon3 cc_mon2 cc_mon1 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 2 : cc_mon3 it indicates that the coulomb counter goes below the battery capacity monitor threshold 3. bit 1 : cc_mon2 it indicates that the coulomb counter goes below the battery capacity monitor threshold 2. bit 0 : cc_mon1 it indicates that the coulomb counter goes below the battery capacity monitor threshold 1. 74h address 73h: cc_batcap3_th_l register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_batcap3_th_l r/w initial value (master mode) 1fh 0 0 0 1 1 1 1 1 initial value (slave mode) 1fh 0 0 0 1 1 1 1 1 cc_batcap3_th[11:0] battery capacity monitor threshold3 73h cc_batcap3_th[7:0] 71 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 77h: cc_ccntd_1 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_ccntd_1 r/w initial value (master mode) xxh x x x x x x x x initial value (slave mode) 00h 0 0 0 0 0 0 0 0 77h ccntd[15:8] address 78h: cc_ccntd_0 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_ccntd_0 r/w initial value (master mode) xxh x x x x x x x x initial value (slave mode) 00h 0 0 0 0 0 0 0 0 ccntd[27:0] coulomb counter it indicates the coulomb counter accumulated result. ccntd[27:16] means the battery capacity in 10 [as] (ampere-second) unit, and ccntd[1:0] is always "00". for example, when the battery capacity is 1350 [mah], the register value will be shown as below 1350 [mah] / 1000 [ma/a] x 3600 [s/h] = 4860 [as]. ccntd[27:16] = 4860 / 10 = 486 (1e6h) when ccntenb = "1", the coulomb counter is enabled accumulation of the charge or discharge current value. in the battery charging, the measured current value is added to the coulomb counter at every conversion period. before starting the battery charging, ccntd must be reset to zero or initialized with an estimated soc (state of charge) value by software. if an empty battery is full-charged, ccntd value indicates the actual battery capacity. this read-only register is able to reset by the register bit ccntrst. in the battery discharging, the coulomb counter decreases the value. before discharging, ccntd must be initialized with batcap value by software, if the remaining battery capacity is unknown. 78h ccntd[7:0] 27 24 23 16 15 8 7 0 10 [as] ccntd[27:0] cc_ccntd_0 cc_ccntd_1 cc_ccntd_2 cc_ccntd_3 address 79h: cc_curcd_u register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_curcd_u r curdir - initial value (master mode) xxh x 0 x x x x x x initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : curdir battery current direction 0 : charging / 1 : discharging 79h curcd[13:8] address 7ah: cc_curcd_l register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_curcd_l r initial value (master mode) xxh x x x x x x x x initial value (slave mode) 00h 0 0 0 0 0 0 0 0 curcd[13:0] battery current value converted from ds-adc output 0 ma to 16,384 ma range, 1 ma units. 7ah curcd[7:0] address 76h: cc_ccntd_2 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_ccntd_2 r/w initial value (master mode) xxh x x x x x x x x initial value (slave mode) 00h 0 0 0 0 0 0 0 0 76h ccntd[23:16] address 75h: cc_ccntd_3 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc_ccntd_3 r/w - - - - initial value (master mode) 0xh 0 0 0 0 x x x x initial value (slave mode) 00h 0 0 0 0 0 0 0 0 75h ccntd[27:24] 72 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 80h: vm_ocur_dur_3 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ocur_dur_3 r/w initial value (master mode) a5h 1 0 1 0 0 1 0 1 initial value (slave mode) a5h 1 0 1 0 0 1 0 1 bit 7-0 : ocurdur3[7:0] the duration time for the battery over-current detection. the value is set in 250 s unit. when currd > ocurthr3 and keeps while ocurdur3 of time length, the register bit ocur3 will be asserted. 80h ocurdur3[7:0] address 7dh: vm_ocur_thr_2 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ocur_thr_2 r/w initial value (master mode) 5eh 0 1 0 1 1 1 1 0 initial value (slave mode) 5eh 0 1 0 1 1 1 1 0 bit 7-0 : ocurthr2[7:0] battery over-current threshold the value is set in 50 ma unit. 7dh ocurthr2[7:0] address 7ch: vm_ocur_dur_1 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ocur_dur_1 r/w initial value (master mode) 64h 0 1 1 0 0 1 0 0 initial value (slave mode) 64h 0 1 1 0 0 1 0 0 bit 7-0 : ocurdur1[7:0] the duration time for the battery over-current detection the value is set in 250 s unit. 7ch ocurdur1[7:0] address 7fh: vm_ocur_thr_3 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ocur_thr_3 r/w initial value (master mode) 4eh 0 1 0 0 1 1 1 0 initial value (slave mode) 4eh 0 1 0 0 1 1 1 0 bit 7-0 : ocurthr3[7:0] battery over-current threshold the value is set in 50 ma unit. 7fh ocurthr3[7:0] address 7eh: vm_ocur_dur_2 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ocur_dur_2 r/w initial value (master mode) 8ch 1 0 0 0 1 1 0 0 initial value (slave mode) 8ch 1 0 0 0 1 1 0 0 bit 7-0 : ocurdur2[7:0] the duration time for the battery over-current detection the value is set in 250 s unit. when currd > ocurthr2 and keeps while ocurdur1 of time length, the register bit ocur2 will be asserted. 7eh ocurdur2[7:0] address 7bh: vm_ocur_thr_1 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ocur_thr_1 r/w initial value (master mode) 7dh 0 1 1 1 1 1 0 1 initial value (slave mode) 7dh 0 1 1 1 1 1 0 1 bit 7-0 : ocurthr1[7:0] battery over-current threshold the value is set in 50 ma unit. 7bh ocurthr1[7:0] 73 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 84h: vm_btmp_lo_thr register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_btmp_lo_thr r/w initial value (master mode) c8h 1 1 0 0 1 0 0 0 initial value (slave mode) c8h 1 1 0 0 1 0 0 0 bit 7-0 : lobtmpthr[7:0] battery low-temperature threshold the value is set in 1-degree unit, -55 to 200 degree range. 84h lobtmpthr[7:0] address 83h: vm_btmp_ov_dur register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_btmp_ov_dur r/w initial value (master mode) 28h 0 0 1 0 1 0 0 0 initial value (slave mode) 28h 0 0 1 0 1 0 0 0 bit 7-0 : ovbtmpdur[7:0] the duration time for the battery over-temperature detection the value is set in 250 us unit. when btmpd > ovtmpthr and keeps while ovtmpdur of time length, the register bit ovtmp will be asserted. 83h ovbtmpdur[7:0] address 82h: vm_btmp_ov_thr register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_btmp_ov_thr r/w initial value (master mode) 8ch 1 0 0 0 1 1 0 0 initial value (slave mode) 8ch 1 0 0 0 1 1 0 0 bit 7-0 : ovbtmpthr[7:0] battery over-temperature threshold the value is set in 1-degree unit, -55 to 200 degree range. 82h ovbtmpthr[7:0] address 81h: vm_ocur_mon register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_ocur_mon r - - - - - ocur3 ocur2 ocur1 initial value (master mode) 0xh 0 0 0 0 0 x x x initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 2 : ocur3 battery over-current 3 detection status 0 : not detected / 1 : detected bit 1 : ocur2 battery over-current 2 detection status 0 : not detected / 1 : detected bit 0 : ocur1 battery over-current 1 detection status 0 : not detected / 1 : detected 81h address 86h: vm_btmp_mon register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_btmp_mon r - - - - - - ovbtmp lobtmp initial value (master mode) 0xh 0 0 0 0 0 0 x x initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 1 : ovbtmp battery over-temperature detection status 0 : not detected / 1 : detected bit 0 : lobtmp battery low-temperature detection status 0 : not detected / 1 : detected 86h address 85h: vm_btmp_lo_dur register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 vm_btmp_lo_dur r/w initial value (master mode) 28h 0 0 1 0 1 0 0 0 initial value (slave mode) 28h 0 0 1 0 1 0 0 0 bit 7-0 : lobtmpdur[7:0] the duration time for the battery over-temperature detection the value is set in 250 us unit. when btmpd < lotmpthr and keeps while lotmpdur of time length, the register bit lotmp will be asserted. 85h lobtmpdur[7:0] 74 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 88h: int_en_01 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_01 r/w - - - - buck4fault buck3fault buck2fault buck1fault initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 3 : buck4fault enabling interrupt of buck4 input current-limit modified 0 : disable / 1 : enable bit 2 : buck3fault enabling interrupt of buck3 input current-limit modified 0 : disable / 1 : enable bit 1 : buck2fault enabling interrupt of buck2 input current-limit modified 0 : disable / 1 : enable bit 0 : buck1fault enabling interrupt of buck1 input current-limit modified 0 : disable / 1 : enable 88h address 89h: int_en_02 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_02 r/w - - dcin_ov_det dcin_ov_res dcin_clps_in dcin_clps_out dcin_rmv - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 5 : dcin_ov_det enabling interrupt of dcin over-voltage detected 0 : disable / 1 : enable bit 4 : dcin_ov_res enabling interrupt of dcin over-voltage resumed 0 : disable / 1 : enable bit 3 : dcin_clps_in enabling interrupt of entering to dcin anti-collapse operation 0 : disable / 1 : enable bit 2 : dcin_clps_out enabling interrupt of exit from dcin anti-collapse operation 0 : disable / 1 : enable bit 1 : dcin_rmv enabling interrupt of dcin removal 0 : disable / 1 : enable 89h address 8ah: int_en_03 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_03 r/w - - - - - - dcin_mon_det dcin_mon_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 1 : dcin_mon_det enabling interrupt of dcin monitor detected 0 : disable / 1 : enable bit 0 : dcin_mon_res enabling interrupt of dcin monitor resumed 0 : disable / 1 : enable 8ah address 8ch: int_en_05 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_05 r/w chg_trns tmp_trns bat_mnt_in bat_mnt_out chg_wdt_exp extemp_tout - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : chg_trns enabling interrupt of charger-state transition 0 : disable / 1 : enable bit 6 : tmp_trns enabling interrupt of temperature range transition 0 : disable / 1 : enable bit 5 : bat_mnt_in enabling interrupt of entering to battery maintenance charging 0 : disable / 1 : enable bit 4 : bat_mnt_out enabling interrupt of exit from battery maintenance charging 0 : disable / 1 : enable bit 3 : chg_wdt_exp enabling interrupt of charger watchdog timer expired 0 : disable / 1 : enable bit 2 : extemp_tout enabling interrupt of timeout in the temperature over-range 0 : disable / 1 : enable 8ch address 8bh: int_en_04 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_04 r/w vsys_mon_det vsys_mon_res - - vsys_lo_det vsys_lo_res vsys_uv_det vsys_uv_res initial value (master mode) 08h 0 0 0 0 1 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : vsys_mon_det enabling interrupt of vsys monitor detected 0 : disable / 1 : enable bit 6 : vsys_mon_res enabling interrupt of vsys monitor resumed 0 : disable / 1 : enable bit 3 : vsys_lo_det enabling interrupt of vsys low-voltage detected 0 : disable / 1 : enable bit 2 : vsys_lo_res enabling interrupt of vsys low-voltage resumed 0 : disable / 1 : enable bit 1 : vsys_uv_det enabling interrupt of vsys under-voltage detected 0 : disable / 1 : enable bit 0 : vsys_uv_res enabling interrupt of vsys under-voltage resumed 0 : disable / 1 : enable 8bh 75 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 8eh: int_en_07 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_07 r/w vbat_ov_det vbat_ov_res vbat_lo_det vbat_lo_res vbat_sht_det vbat_sht_res dbat_det - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : vbat_ov_det enabling interrupt of vbat over-voltage detected 0 : disable / 1 : enable bit 6 : vbat_ov_res enabling interrupt of vbat over-voltage resumed 0 : disable / 1 : enable bit 5 : vbat_lo_det enabling interrupt of vbat low-voltage detected 0 : disable / 1 : enable bit 4 : vbat_lo_res enabling interrupt of vbat low-voltage resumed 0 : disable / 1 : enable bit 3 : vbat_sht_det enabling interrupt of vbat short-circuit detected 0 : disable / 1 : enable bit 2 : vbat_sht_res enabling interrupt of vbat short-circuit resumed 0 : disable / 1 : enable bit 1 : dbat_det enabling interrupt of dead-battery detected 0 : disable / 1 : enable 8eh address 91h: int_en_10 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_10 r/w - - ocur3_det ocur3_res ocur2_det ocur2_res ocur1_det ocur1_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 5 : ocur3_det enabling interrupt of battery over-current 3 detected 0 : disable / 1 : enable bit 4 : ocur3_res enabling interrupt of battery over-current 3 resumed 0 : disable / 1 : enable bit 3 : ocur2_det enabling interrupt of battery over-current 2 detected 0 : disable / 1 : enable bit 2 : ocur2_res enabling interrupt of battery over-current 2 resumed 0 : disable / 1 : enable bit 1 : ocur1_det enabling interrupt of battery over-current 1 detected 0 : disable / 1 : enable bit 0 : ocur1_res enabling interrupt of battery over-current 1 resumed 0 : disable / 1 : enable 91h address 8dh: int_en_06 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_06 r/w th_det th_rmv bat_det bat_rmv - - tmp_out_det tmp_out_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : th_det enabling interrupt of the thermistor detected 0 : disable / 1 : enable bit 6 : th_rmv enabling interrupt of the thermistor removal 0 : disable / 1 : enable bit 5 : bat_det enabling interrupt of the battery detected 0 : disable / 1 : enable bit 4 : bat_rmv enabling interrupt of the battery removed 0 : disable / 1 : enable bit 1 : tmp_out_det enabling interrupt of the temperature out of the charging range 0 : disable / 1 : enable bit 0 : tmp_out_res enabling interrupt of the temperature in to the charging range 0 : disable / 1 : enable 8dh address 90h: int_en_09 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_09 r/w - - - - - cc8th_det cc4th_det cc2nd_det initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 2 : cc8th_det enabling interrupt of under 1/8 capacity discharging 0 : disable / 1 : enable bit 1 : cc4th_det enabling interrupt of under 1/4 capacity discharging 0 : disable / 1 : enable bit 0 : cc2nd_det enabling interrupt of under 1/2 capacity discharging 0 : disable / 1 : enable 90h address 8fh: int_en_08 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_08 r/w - - - - - - vbat_mon_det vbat_mon_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 1 : vbat_mon_det enabling interrupt of vbat monitor1 detected 0 : disable / 1 : enable bit 0 : vbat_mon_res enabling interrupt of vbat monitor1 resumed 0 : disable / 1 : enable 8fh 76 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 92h: int_en_11 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_11 r/w vf_det vf_res vf125_det vf125_res ovtmp_det ovtmp_res lotmp_det lotmp_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 : vf_det enabling interrupt of the vf detected 0 : disable / 1 : enable bit 6 : vf_res enabling interrupt of the vf resumed 0 : disable / 1 : enable bit 5 : vf125_det enabling interrupt of the vf at 125 detected 0 : disable / 1 : enable bit 4 : vf125_res enabling interrupt of the vf at 125 resumed 0 : disable / 1 : enable bit 3 : ovtmp_det enabling interrupt of the battery over-temperature detected 0 : disable / 1 : enable bit 2 : ovtmp_res enabling interrupt of the battery over-temperature resumed 0 : disable / 1 : enable bit 1 : lotmp_det enabling interrupt of the battery low-temperature detected 0 : disable / 1 : enable bit 0 : lotmp_res enabling interrupt of the battery low-temperature resumed 0 : disable / 1 : enable 92h address 94h: int_stat register (r) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat r buck_ast dcin_ast vsys_ast chg_ast bat_ast bmon_ast tmp_ast alm_ast initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7(r) : buckast merged status of int_stat_01 0 : no event / 1 : event occurred bit 7(w) : buckast global reset for int_stat_01 0 : not reset / 1 : reset writing "1" resets all bits of int_stat_01 at once. indicates the read data from the all bits of int_stat_01. bit 6(r) : dcinast merged status of int_stat_02-03 0 : no event / 1 : event occurred bit 6(w) : dcinast global reset for int_stat_02-03 0 : not reset / 1 : reset writing "1" resets all bits of int_stat_02-03 at once. indicates the read data from the all bits of int_stat_02-03. bit 5(r) : vsysast merged status of int_stat_04 0 : no event / 1 : event occurred bit 5(w) : vsysast global reset for int_stat_04 0 : not reset / 1 : reset writing "1" resets all bits of int_stat_04 at once. indicates the read data from the all bits of int_stat_04. bit 4(r) : chgast merged status of int_stat_05 0 : no event / 1 : event occurred bit 4(w) : chgast global reset for int_stat_05 0 : not reset / 1 : reset writing "1" resets all bits of int_stat_05 at once. indicates the read data from the all bits of int_stat_05. bit 3(r) : batast merged status of int_stat_06 0 : no event / 1 : event occurred bit 3(w) : batast global reset for int_stat_06of int_stat_06. 0 : not reset / 1 : reset writing "1" resets all bits of int_stat_06 at once. indicates the read data from the all bits of int_stat_06. bit 2(r) : bmonast merged status of int_stat_07-10 0 : no event / 1 : event occurred bit 2(w) : bmonast global reset for int_stat_07-10 0 : not reset / 1 : reset writing "1" resets all bits of int_stat_07-10 at once. indicates the read data from the all bits of int_stat_07-10. bit 1(r) : tmpast merged status of int_stat_11 0 : no event / 1 : event occurred bit 1(w) : tmpast global reset for int_stat_11 0 : not reset / 1 : reset writing "1" resets all bits of int_stat_11 at once. indicates the read data from the all bits of int_stat_11. bit 0(r) : almast merged status of int_stat_12 0 : no event / 1 : event occurred bit 0(w) : almast global reset for int_stat_12 0 : not reset / 1 : reset writing "1" resets all bits of int_stat_12 at once. indicates the read data from the all bits of int_stat_12. 94h address 93h: int_en_12 register (r/w) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_en_12 r/w - - - - - alm2 alm1 alm0 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 2 : alm2 enabling interrupt of the alarm2 resumed 0 : disable / 1 : enable bit 1 : alm1 enabling interrupt of the alarm1 resumed 0 : disable / 1 : enable bit 0 : alm0 enabling interrupt of the alarm0 resumed 0 : disable / 1 : enable 93h 77 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 97h: int_stat_03 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_03 r/wc - - - - - - dcin_mon_det dcin_mon_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 1 (r) : dcin_mon_det interrupt clear for status of dcin voltage monitor detected 0 : no event / 1 : event occurred bit 1 (w) : dcin_mon_det interrupt status of dcin voltage monitor detected 0 : not reset / 1 : reset bit 0 (r) : dcin_mon_res interrupt status of dcin voltage monitor resumed 0 : no event / 1 : event occurred bit 0 (w) : dcin_mon_res interrupt clear for status of dcin voltage monitor resumed 0 : not reset / 1 : reset 97h address 96h: int_stat_02 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_02 r/wc - - dcin_ov_det dcin_ov_res dcin_clps_in dcin_clps_out dcin_rmv - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 5 (r) : dcin_ov_det interrupt status of dcin over-voltage detected 0 : no event / 1 : event occurred bit 5 (w) : dcin_ov_det interrupt clear for status of dcin over-voltage detected 0 : not reset / 1 : reset bit 4 (r) : dcin_ov_res interrupt status of dcin over-voltage resumed 0 : no event / 1 : event occurred bit 4 (w) : dcin_ov_res interrupt clear for status of dcin over-voltage resumed 0 : not reset / 1 : reset bit 3 (r) : dcin_clps_in interrupt status of entering to dcin anti-collapse op 0 : no event / 1 : event occurred bit 3 (w) : dcin_clps_in interrupt clear for status of entering to dcin anti-collapse op 0 : not reset / 1 : reset bit 2 (r) : dcin_clps_out interrupt status of exit from dcin anti-collapse op 0 : no event / 1 : event occurred bit 2 (w) : dcin_clps_out interrupt clear for status of exit from dcin anti-collapse op 0 : not reset / 1 : reset bit 1 (r) : dcin_rmv interrupt status of dcin removal 0 : no event / 1 : event occurred bit 1 (w) : dcin_rmv interrupt clear for status of dcin removal 0 : not reset / 1 : reset 96h address 95h: int_stat_01 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_01 r/wc - - - - buck4fault buck3fault buck2fault buck1fault initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 3 (r) : buck4fault interrupt status of entering to buck4 current limit operation 0 : no event / 1 : event occurred bit 3 (w) : buck4fault interrupt clear fof status of buck4 current-limit operation 0 : not reset / 1 : reset bit 2 (r) : buck3fault interrupt status of entering to buck3 current limit operation 0 : no event / 1 : event occurred bit 2 (w) : buck3fault interrupt clear fof status of buck3 current-limit operation 0 : not reset / 1 : reset bit 1 (r) : buck2fault interrupt status of entering to buck2 current limit operation 0 : no event / 1 : event occurred bit 1 (w) : buck2fault interrupt clear fof status of buck2 current-limit operation 0 : not reset / 1 : reset bit 0 (r) : buck1fault interrupt status of entering to buck1 current limit operation 0 : no event / 1 : event occurred bit 0 (w) : buck1fault interrupt clear fof status of buck1 current-limit operation 0 : not reset / 1 : reset 95h address 98h: int_stat_04 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_04 r/wc vsys_mon_det vsys_mon_res - - vsys_lo_det vsys_lo_res vsys_uvdet vsys_uv_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 (r) : vsys_mon_det interrupt status of vsys voltage monitor detected 0 : no event / 1 : event occurred bit 7 (w) : vsys_mon_det interrupt clear for status of vsys voltage monitor detected 0 : not reset / 1 : reset bit 6 (r) : vsys_mon_res interrupt status of vsys voltage monitor resumed 0 : no event / 1 : event occurred bit 6 (w) : vsys_mon_res interrupt clear for status of vsys voltage monitor resumed 0 : not reset / 1 : reset bit 3 (r) : vsys_lo_det interrupt status of vsys low-voltage detected 0 : no event / 1 : event occurred bit 3 (w) : vsys_lo_det interrupt clear for status of vsys low-voltage detected 0 : not reset / 1 : reset bit 2 (r) : vsys_lo_res interrupt status of vsys low-voltage resumed 0 : no event / 1 : event occurred bit 2 (w) : vsys_lo_res interrupt clear for status of vsys low-voltage resumed 0 : not reset / 1 : reset bit 1 (r) : vsys_uvdet interrupt status of vsys under-voltage detected 0 : no event / 1 : event occurred bit 1 (w) : vsys_uvdet interrupt clear for status of vsys under-voltage detected 0 : not reset / 1 : reset bit 0 (r) : vsys_uv_res interrupt status of vsys under-voltage resumed 0 : no event / 1 : event occurred bit 0 (w) : vsys_uv_res interrupt clear for status of vsys under-voltage resumed 0 : not reset / 1 : reset 98h 78 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 9bh: int_stat_07 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_07 r/wc vbat_ov_det vbat_ov_res vbat_lo_det vbat_lo_res vbat_sht_det vbat_sht_res dbat_det - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 (r) : vbat_ov_det interrupt status of vbat over-voltage detected 0 : no event / 1 : event occurred bit 7 (w) : vbat_ov_det interrupt clear for status of vbat over-voltage detected 0 : not reset / 1 : reset bit 6 (r) : vbat_ov_res interrupt status of vbat over-voltage resumed 0 : no event / 1 : event occurred bit 6 (w) : vbat_ov_res interrupt clear for status of vbat over-voltage resumed 0 : not reset / 1 : reset bit 5 (r) : vbat_lo_det interrupt status of vbat low-voltage detected 0 : no event / 1 : event occurred bit 5 (w) : vbat_lo_det interrupt clear for status of vbat low-voltage detected 0 : not reset / 1 : reset bit 4 (r) : vbat_lo_res interrupt status of vbat low-voltage resumed 0 : no event / 1 : event occurred bit 4 (w) : vbat_lo_res interrupt clear for status of vbat low-voltage resumed 0 : not reset / 1 : reset bit 3 (r) : vbat_sht_det interrupt status of vbat short-circuit detected 0 : no event / 1 : event occurred bit 3 (w) : vbat_sht_det interrupt clear for status of vbat short-circuit detected 0 : not reset / 1 : reset bit 2 (r) : vbat_sht_res interrupt status of vbat short-circuit resumed 0 : no event / 1 : event occurred bit 2 (w) : vbat_sht_res interrupt clear for status of vbat short-circuit resumed 0 : not reset / 1 : reset bit 1 (r) : dbat_det interrupt status of dead-battery detected 0 : no event / 1 : event occurred bit 1 (w) : dbat_det interrupt clear for status of dead-battery detected 0 : not reset / 1 : reset 9bh address 9ah: int_stat_06 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_06 r/wc th_det th_rmv bat_det bat_rmv - - tmp_out_det tmp_out_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 (r) : th_det interrupt status of the thermistor detected 0 : no event / 1 : event occurred bit 7 (w) : th_det interrupt clear for status of the thermistor detected 0 : not reset / 1 : reset bit 6 (r) : th_rmv interrupt status of the thermistor removal 0 : no event / 1 : event occurred bit 6 (w) : th_rmv interrupt clear for status of the thermistor removal 0 : not reset / 1 : reset bit 5 (r) : bat_det interrupt status of the battery detected 0 : no event / 1 : event occurred bit 5 (w) : bat_det interrupt clear for status of the battery detected 0 : not reset / 1 : reset bit 4 (r) : bat_rmv interrupt status of the battery removed 0 : no event / 1 : event occurred bit 4 (w) : bat_rmv interrupt clear for status of the battery removed 0 : not reset / 1 : reset bit 1 (r) : tmp_out_det interrupt status of the temperature out of the charging range 0 : no event / 1 : event occurred bit 1 (w) : tmp_out_det interrupt clear for status of the temperature out of the charging range 0 : not reset / 1 : reset bit 0 (r) : tmp_out_res interrupt status of the temperature in to the charging range 0 : no event / 1 : event occurred bit 0 (w) : tmp_out_res interrupt clear for status of the temperature in to the charging range 0 : not reset / 1 : reset 9ah address 99h: int_stat_05 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_05 r/wc chg_trns tmp_trns bat_mnt_in bat_mnt_out chg_wdt_exp extemp_tout - - initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 (r) : chg_trns interrupt status of charger-state transition 0 : no event / 1 : event occurred bit 7 (w) : chg_trns interrupt clear for status of charger-state transition 0 : not reset / 1 : reset bit 6 (r) : tmp_trns interrupt status of temperature range transition 0 : no event / 1 : event occurred bit 6 (w) : tmp_trns interrupt clear for status of temperature range transition 0 : not reset / 1 : reset bit 5 (r) : bat_mnt_in interrupt status of entering to battery maintenance charging 0 : no event / 1 : event occurred bit 5 (w) : bat_mnt_in interrupt clear for status of entering to battery maintenance charging 0 : not reset / 1 : reset bit 4 (r) : bat_mnt_out interrupt status of exit from battery maintenance charging 0 : no event / 1 : event occurred bit 4 (w) : bat_mnt_out interrupt clear for status of exit from battery maintenance charging 0 : not reset / 1 : reset bit 3 (r) : chg_wdt_exp interrupt status of charger watchdog timer expired 0 : no event / 1 : event occurred bit 3 (w) : chg_wdt_exp interrupt clear for status of charger watchdog timer expired 0 : not reset / 1 : reset bit 2 (r) : extemp_tout interrupt status of timeout in the temperature over-range 0 : no event / 1 : event occurred bit 2 (w) : extemp_tout interrupt clear for status of timeout in the temperature over-range 0 : not reset / 1 : reset 99h 79 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address 9eh: int_stat_10 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_10 r/wc - - ocur3_det ocur3_res ocur2_det ocur2_res ocur1_det ocur1_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 5 (r) : ocur3_det interrupt status of battery over-current 3 detected 0 : no event / 1 : event occurred bit 5 (w) : ocur3_det interrupt clear for status of battery over-current 3 detected 0 : not reset / 1 : reset bit 4 (r) : ocur3_res interrupt status of battery over-current 3 resumed 0 : no event / 1 : event occurred bit 4 (w) : ocur3_res interrupt clear for status of battery over-current 3 resumed 0 : not reset / 1 : reset bit 3 (r) : ocur2_det interrupt status of battery over-current 2 detected 0 : no event / 1 : event occurred bit 3 (w) : ocur2_det interrupt clear for status of battery over-current 2 detected 0 : not reset / 1 : reset bit 2 (r) : ocur2_res interrupt status of battery over-current 2 resumed 0 : no event / 1 : event occurred bit 2 (w) : ocur2_res interrupt clear for status of battery over-current 2 resumed 0 : not reset / 1 : reset bit 1 (r) : ocur1_det interrupt status of battery over-current 1 detected 0 : no event / 1 : event occurred bit 1 (w) : ocur1_det interrupt clear for status of battery over-current 1 detected 0 : not reset / 1 : reset bit 0 (r) : ocur1_res interrupt status of battery over-current 1 resumed 0 : no event / 1 : event occurred bit 0 (w) : ocur1_res interrupt clear for status of battery over-current 1 resumed 0 : not reset / 1 : reset 9eh address 9dh: int_stat_09 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_09 r/wc - - - - - cc8th_det cc4th_det cc2nd_det initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 2 (r) : cc8th_det interrupt status of under 1/8 capacity discharging 0 : no event / 1 : event occurred bit 2 (w) : cc8th_det interrupt clear for status of under 1/8 capacity discharging 0 : not reset / 1 : reset bit 1 (r) : cc4th_det interrupt status of under 1/4 capacity discharging 0 : no event / 1 : event occurred bit 1 (w) : cc4th_det interrupt clear for status of under 1/4 capacity discharging 0 : not reset / 1 : reset bit 0 (r) : cc2nd_det interrupt status of under 1/2 capacity discharging 0 : no event / 1 : event occurred bit 0 (w) : cc2nd_det interrupt clear for status of under 1/2 capacity discharging 0 : not reset / 1 : reset 9dh address 9ch: int_stat_08 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_08 r/wc - - - - - - vbat_mon_det vbat_mon_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 1 (r) : vbat_mon_det interrupt status of vbat monitor detected 0 : no event / 1 : event occurred bit 1 (w) : vbat_mon_det interrupt clear for status of vbat monitor detected 0 : not reset / 1 : reset bit 0 (r) : vbat_mon_res interrupt status of vbat monitor resumed 0 : no event / 1 : event occurred bit 0 (w) : vbat_mon_res interrupt clear for status of vbat monitor resumed 0 : not reset / 1 : reset 9ch 80 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv address a1h: int_update register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_update r/wc - - - - - - - int_update initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 0 : int_update the present interruption status is updated. 0 : interruption is not updated. 1 : interruption is updated. a1h address a0h: int_stat_12 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_12 r/wc - - - - - alm2 alm1 alm0 initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 2 (r) : alm2 interrupt status of the alarm2 resumed 0 : no event / 1 : event occurred bit 2 (w) : alm2 interrupt clear for status of the alarm2 resumed 0 : not reset / 1 : reset bit 1 (r) : alm1 interrupt status of the alarm1 resumed 0 : no event / 1 : event occurred bit 1 (w) : alm1 interrupt clear for status of the alarm1 resumed 0 : not reset / 1 : reset bit 0 (r) : alm0 interrupt status of the alarm0 resumed 0 : no event / 1 : event occurred bit 0 (w) : alm0 interrupt clear for status of the alarm0 resumed 0 : not reset / 1 : reset a0h address 9fh: int_stat_11 register (r/wc) address (index) register name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 int_stat_11 r/wc vf_det vf_res vf125_det vf125_res ovtmp_det ovtmp_res lotmp_det lotmp_res initial value (master mode) 00h 0 0 0 0 0 0 0 0 initial value (slave mode) 00h 0 0 0 0 0 0 0 0 bit 7 (r) : vf_det interrupt status of thermal regulation detected 0 : no event / 1 : event occurred bit 7 (w) : vf_det interrupt clear for status of thermal regulation detected 0 : not reset / 1 : reset bit 6 (r) : vf_res interrupt status of thermal regulation resumed 0 : no event / 1 : event occurred bit 6 (w) : vf_res interrupt clear for status of thermal regulation resumed 0 : not reset / 1 : reset bit 6 (r) : vf125_det interrupt status of thermal regulation at 125 resumed 0 : no event / 1 : event occurred bit 6 (w) : vf125_det interrupt clear for status of thermal regulation at 125 resumed 0 : not reset / 1 : reset bit 6 (r) : vf125_res interrupt status of thermal regulation at 125 resumed 0 : no event / 1 : event occurred bit 6 (w) : vf125_res interrupt clear for status of thermal regulation at 125 resumed 0 : not reset / 1 : reset bit 3 (r) : ovtmp_det interrupt status of the battery over-temperature detected 0 : no event / 1 : event occurred bit 3 (w) : ovtmp_det interrupt clear for status of the battery over-temperature detected 0 : not reset / 1 : reset bit 2 (r) : ovtmp_res interrupt status of the battery over-temperature resumed 0 : no event / 1 : event occurred bit 2 (w) : ovtmp_res interrupt clear for status of the battery over-temperature resumed 0 : not reset / 1 : reset bit 1 (r) : lotmp_det interrupt status of the battery low-temperature detected 0 : no event / 1 : event occurred bit 1 (w) : lotmp_det interrupt clear for status of the battery low-temperature detected 0 : not reset / 1 : reset bit 0 (r) : lotmp_res interrupt status of the battery low-temperature resumed 0 : no event / 1 : event occurred bit 0 (w) : lotmp_res interrupt clear for status of the battery low-temperature resumed 0 : not reset / 1 : reset 9fh 81 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv i/o equivalen t circuit s e : s c l v i n s n v s c a p f : s d a a : p w r o n v i n b : s t a n d b y c : r e s e t i n b 1 . 5 m 1 . 5 m 1 . 5 m s n v s c a p 1 0 k s n v s c a p d : m s s e l g : l x 1 , l x 2 , l x 3 , l x 4 p v i n h : f b 1 , f b 2 , f b 3 , f b 4 d v d d d v d d 1 0 k v i n 1 0 k 1 0 k 1 0 k 1 k 1 k 1 0 6 0 0 2 m 82 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv i/o equivalent circuits - continued m : g p o 1 , 2 , 3 , c l k 3 2 k o u t n : p o r , i n t b , c h g l e d i : v i n l 1 , v o 1 j : v i n l 2 , v o 2 , v o 3 k : d v r e f i n l : v o d v r e f o : x i n 3 2 k , x o u t 3 2 k p : s n v s c a p , v o s n v s v i n v i n s n v s c a p x i n 3 2 k x o u t 3 2 k s n v s c a p 1 9 m 1 0 k 1 0 k s n v s c a p v i n v o s n v s v i n l 1 v o 1 v i n v i n l 2 v o 2 , v o 3 6 0 0 3 m 3 m 6 0 0 4 m 6 0 0 2 m 2 0 1 5 m 2 0 k 83 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv i/o equivalent circuits - continued t : d c i n , v s y s , v b a t , c p o u t q : c h g r e f r : t s s : b a t t p , b a t t m s n v s c a p d c i n v s y s v b a t c p o u t 4 m 3 0 k 1 0 k 2 0 2 0 0 k 5 0 0 k 1 0 k 1 0 k 2 . 5 k 2 0 0 1 0 k u : d v d d v i n 2 0 0 k s n v s 84 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv t ypical performance curves figure 26 . battery current vs battery voltage (off mode, master mode ) figure 27 . battery current vs battery voltage (off mode, slave mode ) figure 28 . battery current vs battery voltage (on mode, master mode ) figure 29 . battery current vs battery voltage (on mode, slave mode ) ta=25 c ta=25 c ta=25 c ta=25 c 0 10 20 30 40 50 0 1 2 3 4 5 6 battery voltage : vbat [v] battery current : icc(off) [a] 0 5 10 15 20 25 0 1 2 3 4 5 6 battery voltage : vbat [v] battery current : icc(on) [ma] 0 10 20 30 40 50 0 1 2 3 4 5 6 battery voltage : vbat[v] battery current : icc(off) [a] 0 5 10 15 20 25 0 1 2 3 4 5 6 battery voltage : vbat [v] battery current : icc(on) [ma] 85 / 96 tsz02201 - 0q4q0ab00050 - 1 - 2 ? 20 15 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv t ypical performance curves - continued figure 30 . battery current vs battery voltage (standby mode, master mode ) figure 31 . battery current vs battery voltage (standby mode, slave mode ) figure 32 . battery current vs battery voltage (sleep mode, master mode ) ta=25 c ta=25 c ta=25 c 0 25 50 75 100 125 150 175 200 0 1 2 3 4 5 6 battery voltage : vbat [v] battery current : icc(standby) [a] 0 25 50 75 100 125 150 175 200 0 1 2 3 4 5 6 battery voltage : vbat [v] battery current : icc(standby) [a] 0 25 50 75 100 125 150 175 200 0 1 2 3 4 5 6 battery voltage : vbat [v] battery current : icc(sleep) [a] 86 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 b d71805mwv t ypical performance curve s - contin ued figure 33 . buck1 C efficien cy (auto mode ) figure 34 . buck1 C efficiency ( pwm mode / pfm mode ) figure 35 . buck2 C efficien cy ( auto mode ) figure 36 . buck2 C efficiency ( pwm mode / pfm mode ) vbat=4.2v, vout=1.2v , ta=25 c vbat=4.2v, vout=1.2v , ta=25 c vbat=4.2v, vo ut =1.425v , ta=25 c pf m mode pw m mode pw m mode pf m mode vbat=4.2v, vo ut =1.425v , ta=25 c 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 10.000 buck1 output curent : io [a] buck1 efficiency : [%] 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 buck2 output current : iout [a] buck2 efficiency : [%] 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 buck2 output current : iout [a] buck2 efficiency : [%] 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 10.000 buck1 output current : iout [a] buck1 efficiency : [%] 87 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv t ypical perform ance curve s - continued figure 3 7 . buck3 C efficien cy ( auto mode ) figure 3 8 . buck3 C efficiency ( pwm mode / pfm mode ) figure 3 9 . buck4 C efficien cy ( auto mode ) figure 40 . buck4 C efficiency ( pwm mode / pfm mode ) vbat=4.2v, vout=1.8v, ta=25 c vbat=4.2v, vout=1.8v, ta=25 c vbat=4.2v, vout=3.3v, ta=25 c vbat=4.2v, vout=3.3v, ta=25 c pf m mode pw m mode pw m mode pf m mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 buck3 output current : iout [a] buck3 efficiency : [%] 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 buck4 output current : iout [a] buck4 efficiency : [%] 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 buck3 output current : iout [a] buck3 efficiency : [%] 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 buck4 output current : iout [a] buck4 efficiency : [%] 88 / 96 tsz02201 - 0q4q0 ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv t ypical performance curves - continued figure 4 1 . buck1 - load regulation ( pwm mode ) figure 4 2 . buck2 - load regulation ( pwm mode ) figure 4 3 . buck3 - load regulation ( pwm mode ) figure 4 4 . buck4 - load regulation ( pwm mode ) vbat=4.2v, ta=25 c vbat=4.2v, ta=25 c vbat=4.2v, ta=25 c vbat=4.2v, ta=25 c 1.70 1.75 1.80 1.85 1.90 0.0 0.2 0.4 0.6 0.8 1.0 buck4 output current : iout [a] buck4 output voltage : vout [v] 3.20 3.25 3.30 3.35 3.40 0.0 0.2 0.4 0.6 0.8 1.0 buck3 output current : iout [a] buck3 output voltage : vout [v] 1.10 1.15 1.20 1.25 1.30 0.0 0.2 0.4 0.6 0.8 1.0 buck2 output current : iout [a] buck2 output voltage : vout [v] 1.325 1.375 1.425 1.475 1.525 0.0 0.4 0.8 1.2 1.6 2.0 buck1 output current : iout [a] buck1 output voltage : vout [v] 89 / 96 tsz02201 - 0q4q0ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 bd71805 mwv t ypical performance curve s - continued figure 4 5 . buck1 - load regulation ( auto mode ) figure 4 6 . buck2 - load regulation ( auto mode ) figure 4 7 . buck3 - load regulation ( auto mode ) figure 4 8 . buck4 - load regulation ( auto mode ) vbat=4.2v, ta=25 c vbat=4.2v, ta=25 c vbat=4.2v, ta=25 c vbat=4.2v, ta=25 c 3.20 3.25 3.30 3.35 3.40 0.0 0.2 0.4 0.6 0.8 1.0 buck3 output current : iout [a] buck3 output voltage : vout [v] 1.70 1.75 1.80 1.85 1.90 0.0 0.2 0.4 0.6 0.8 1.0 buck4 output current : iout [a] buck4 output voltage : vout [v] 1.325 1.375 1.425 1.475 1.525 0.0 0.4 0.8 1.2 1.6 2.0 buck1 output current : iout [a] buck1 output voltage : vout [v] 1.10 1.15 1.20 1.25 1.30 0.0 0.2 0.4 0.6 0.8 1.0 buck2 output current : iout [a] buck2 output voltage : vout [v] 90 / 96 bd71805 mwv tsz02201 - 0q4q0ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 t ypical performance curves - continued figure 4 9 . ldo1 - load regulation figure 50 . ldo2 - load regulation figure 51 . ldo3 - load regulation vbat=4.2v, ta=25 c vbat=4.2v, ta=25 c vbat=4.2v, ta=25 c 1.10 1.15 1.20 1.25 1.30 0 50 100 150 200 250 300 ldo1 output current : io [ma] ldo1 output voltage : vout [v] 3.20 3.25 3.30 3.35 3.40 0 50 100 150 200 250 300 ldo3 output current : iout [ma] ldo3 output voltage : vout [v] 3.20 3.25 3.30 3.35 3.40 0 50 100 150 200 250 300 ldo2 output current : iout [ma] ldo2 output voltage : vout [v] 91 / 96 bd71805 mwv tsz02201 - 0q4q0ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 .feb.2015 rev.001 www.rohm.com tsz22111 ? 15 ? 001 t ypical performance curves - continued figure 52 . charge cu rrent vs battery voltage figure 53 . dsa - inl vs input voltage figure 54 . sar - dnl vs number of input voltage step figure 55 . sar - inl vs number of input voltage ste dcin=5v, ta=25 c vbat=3.6v, ta=25 c vbat=3.6v, ta=25 c vbat=3.6v, ta=25 c i_fstchg=400ma i_fstchg= 7 00ma i_fstchg= 16 00ma < - discharge c harge - > - 3 - 2 - 1 0 1 2 3 0 512 1024 1536 2048 2560 3072 3584 4096 integaral non - linearity : inl [lsb] number of input voltage step : n - 3 - 2 - 1 0 1 2 3 0 512 1024 1536 2048 2560 3072 3584 4096 differential non - linearity : dnl [lsb] number of input voltage step : n -3 -2 -1 0 1 2 3 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 battery current : ibat [a] integral non-linearity : inl[lsb] 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 battery voltage : vbat [v] charge current : ichg [ma] 92 / 96 tsz02201 - 0q4q0ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 . f eb .201 5 rev.0 0 1 www.rohm.com tsz22111 ? 15 ? 001 b d71805mwv operational notes 1. reverse c onnection of p ower s upply c onnecting the power supply in reverse polarity can damage the ic. take pr ecautions against reverse polarity when connecting the power supply , such as mounting an external diode between the power supply and the ic s power supply terminal s. 2. power s upply l in es design the pcb layout pattern to provide low impedance supply lines. s eparate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block . furthermore, connect a capacitor to ground at all power supply pins . consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. g round voltage ensure that no pins are at a voltage below that of the ground pin at any time , even during transient condition. 4. g round w iring p attern when using both small - signal and large - current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to av oid fluctuations in the small - signal ground caused by large currents. also ensure that the ground traces of external components do not cause variations on the ground voltage. the ground lines must be as short and thick as possible to reduce line impedance. 5. thermal c onsideration should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. the absolute maximum rating of the pd stated in this specification is when the ic is mounted on a 7 4.2 mm x 7 4.2 mm x 1.6 t mm glass epoxy board. in case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the pd rating. 6. recommended o perating c onditions these conditions represent a range within which the expected characteristics of the ic can be approximately obtained . the e lectrical characteristics are guaranteed under the conditions of each parameter . 7. in r ush current when power is first supplied to the ic, it is possible that t he internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the ic has more than one power supply. therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. operation u nder s trong e lectromagnetic f ield operating the ic in the presence of a strong electromagnetic field may cause the ic to malfunction . 9. testing on a pplication b oards when testing the ic on an application board, connecting a capacitor directly to a low - impedance output pin may subject the ic to stress. always discharge capacitors completely after each process or step. the ic s power supply should always be turned off completely before con necting or removing it from the test setup during the inspection process. to prevent damage from static discharge, ground the ic during assembly and use similar precautions during transport and storage. 10. inter - pin short and mounting errors ensure that the direction and position are correct when mounting the ic on the pcb. incorrect mounting may result in damaging the ic. avoid nearby pins being shorted to each other especially to ground , power supply and output pin . inter - pin shorts could be due to many rea sons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 93 / 96 tsz02201 - 0q4q0ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 . f eb .201 5 rev.0 0 1 www.rohm.com tsz22111 ? 15 ? 001 b d71805mwv operational notes C continued 11. unused input terminals input terminals of an ic are often con nected to the gate of a mos transistor. the gate has extremely high impedance and extremely low capacitance. if left unconnected, the electric field from the outside can easily charge it. the small charge acquired in this way is enough to produce a signifi cant effect on the conduction through the transistor and cause unexpected operation of the ic. so unless otherwise specified, unused input terminals should be connected to the power supply or ground line. 12. regarding the i nput p in of the ic this monolithic ic contains p+ isolation and p substrate layers between adjacent elements in order to keep them isolated. p - n junctions are formed at the intersection of the p layers with the n layers of oth er elements, creating a parasitic diode or transistor. for exampl e (refer to figure below): when gnd > pin a and gnd > pin b, the p - n junction operates as a parasitic diode. when gnd > pin b, the p - n junction operates as a parasitic transistor. parasitic diodes inevitably occur in the structure of the ic. the operati on of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. therefore , conditions that cause these diodes to operate, such as applying a voltage lower than the gnd voltage to an input pin (and thus to th e p substrate) should be avoided. fig ure 5 6 . example of monolithic ic structure 13. ceramic capacitor when using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with temperature and the decrease in nominal ca pacitance due to dc bias and others. 14. area of safe operation (aso ) operate the ic such that the output voltage, output current, and power dissipation are all within the area of safe operation (aso). 15. thermal shutdown circuit( tsd) this ic has a built - in thermal shutdown circuit that prevents heat damage to the ic. normal operation should always be within the ics power dissipation rating. if however the rating is exceeded for a continued period, the junction temperature (tj) wi ll rise which will activate the tsd circuit that will turn off all output pins. when the tj falls below the tsd threshold, the circuits are automatically restored to normal operation. note that the tsd circuit operates in a situation that exceeds the absol ute maximum ratings and therefore, under no circumstances, should the tsd circuit be used in a set design or for any purpose other than protecting the ic from heat damage. 16. over c urrent p rotection c ircuit (ocp) this ic incorporates an integrated over - curre nt protection circuit that is activated when the load is shorted. this protection circuit is effective in preventing damage due to sudden and unexpected incidents. however, the ic should not be used in applications characterized by continuous operation or transitioning of the protection circuit. n n p + p n n p + p s u b s t r a t e g n d n p + n n p + n p p s u b s t r a t e g n d g n d p a r a s i t i c e l e m e n t s p i n a p i n a p i n b p i n b b c e p a r a s i t i c e l e m e n t s g n d p a r a s i t i c e l e m e n t s c b e t r a n s i s t o r ( n p n ) r e s i s t o r n r e g i o n c l o s e - b y p a r a s i t i c e l e m e n t s 94 / 96 tsz02201 - 0q4q0ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 . f eb .201 5 rev.0 0 1 www.rohm.com tsz22111 ? 15 ? 001 b d71805mwv ordering information b d 7 1 8 0 5 m w v - e 2 part number package uqfn 64 m v8080 packaging and forming specification e2: embossed tape and reel marking diagram uqfn 64 m v8080 (top view) bd7180 5 part number marking lot number 1pin mark 95 / 96 tsz02201 - 0q4q0ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 . f eb .201 5 rev.0 0 1 www.rohm.com tsz22111 ? 15 ? 001 b d71805mwv physical dimension , tape and reel information package name uqfn64mv8080 96 / 96 tsz02201 - 0q4q0ab00050 - 1 - 2 ? 20 1 5 rohm co., ltd. all rights reserved. 2 7 . f eb .201 5 rev.0 0 1 www.rohm.com tsz22111 ? 15 ? 001 b d71805mwv revision history date revision changes 2 7 . feb .201 5 001 new release notice - p ga - e rev.00 3 ? 201 5 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our p roducts are designed and manufactured for application in ordinary electronic equipment s ( such as av equipment, oa equipment, telecommunication equipment, home elec tronic appliances, amusement equipment, etc.). if you intend to use our products in devices requiring extremely high reliability ( such as medical equipment ( n ote 1 ) , transport equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, f uel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life , bodily injury or serious damage to property ( specific applications ) , please consult with the rohm sales represe ntative in advance. unless otherwise agreed in writing by rohm in advance, rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any rohm s products for specific appl ications. ( n ote1) m edical e quipment c lassification of the s pecific applications japan usa eu china class 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsi bilities, adequate safety measures including but not limited to fail - safe design against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our p roducts are designed and manufactured for use under standard conditions a nd not under any special or extraordinary environments or conditions, as exemplified below . accordingly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any rohms p roduct s under any special or extraordinary environments or conditions . if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent v erification and confirmation of product performance, reliability, etc, pri or to use, must be necessary : [a] use of our products in any types of liquid, including water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the p roducts are exposed to direct sunlight or dust [c] use of our prod ucts in places where the p roducts are exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the p roducts are exposed to static electricity or electromagnetic waves [e] use of our products in p roximity to heat - producing components, plastic cords, or other flammable items [f] s ealing or coating our p roducts with resin or other coating materials [g] use of our products without cleaning residue of flux (even if you use no - clean type fluxes, cleanin g residue of flux is recommended); or washing our products by using water or water - soluble cleaning agents for cleaning residue after soldering [h] use of the p roducts in places subject to dew condensation 4 . the p roducts are not subject to radiation - proo f design . 5 . please verify and confirm characteristics of the final or mounted products in using the products. 6 . in particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of pe rformance characteristics after on - board mounting is strongly recommended. avoid applying power exceeding normal rated power; exceeding the power rating under steady - state loading condition may negatively affect product performance and reliability. 7 . de - rate power dissipation d epending on a mbient temperature . when used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8 . confirm that operation temperature is within the specified range described in the product specification. 9 . rohm shall not be in any way responsible or liable for f ailure induced under devian t condition from what is defined in this document . precaution for mounting / circuit board design 1. when a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used on a surface - mount products, the flow soldering method must be used on a through hole mount products. i f the flow soldering method is preferred on a surface - mount products , please consult with the roh m representative in advance. for details , please refer to rohm mounting specification notice - p ga - e rev.00 3 ? 201 5 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, please allow a sufficient margin considerin g variations of the characteristics of the p roducts and external components, including transient characteristics, as well as static characteristics. 2. you agree that application notes, reference designs, and associated data and information contained in t his document are presented only as guidance for products use . therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in t his document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this p roduct is e lectrostatic sensitive product, which may be damaged due to e lectrostatic discharge. please take proper caution in your manufacturing process and stor age so that voltage exceeding the product s maximum rating will not be applied to p roducts. please take special care under dry condition (e .g. grounding of human body / equipment / solder iron, isolation from charged objects, setting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriorate if the p roducts are stored in the places where : [a] the p roducts are exposed to sea winds or corrosive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to direct sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage condition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm solderability before using p roducts of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the correct direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excess ive stress applied when dropping of a carton. 4. use p roducts within the specified time after opening a humidity barrier bag. baking is required before using p roducts of which storage time is exceeding the recommended storage time period . precaution for p roduct l abel a two - dimensional barcode printed on rohm p roduct s label is for rohm s internal use only . precaution for d isposition when disposing p roducts please dispose them properly using a n authorized industry waste company. precaution for foreign e xchange and foreign t rade act since concerned goods might be fallen under listed items of export control prescribed by foreign exchange and foreign trade act, please consult with rohm in case of export. precaution regarding intellectual property rights 1. all information an d data including but not limited to application example contained in this document is for reference only. rohm does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party reg arding such information or data. 2. rohm shall not have any obligations where the claims, actions or demands arising from the combination of the products with other articles such as components, circuits, systems or external equipment (including software). 3. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the products or the information contained in this document. provided, however, that rohm will not assert it s intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the products, subject to the terms and conditions herein. other precaution 1. this document may not be reprinted or reproduced, in whole or in part, without prior written consent of rohm. 2. the products may not be disassemble d, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. i n no event shall you use in any way whatso ever the products and the related technical information contained in the products or this document for any military purposes , including but not limited to, the development of mass - destruction weapons . 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. datasheet datasheet notice ? we rev.001 ? 2015 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. datasheet part number BD71805MWV package uqfn64mv8080 unit quantity 1000 minimum package quantity 1000 packing type taping constitution materials list inquiry rohs yes BD71805MWV - web page |
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